Multilayer Ceramic Capacitor Asymmetric Width Design
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Solution Overview
Problem
Multilayer ceramic electronic components with increased stacked layers for high capacitance often suffer from defects such as toppling over and tombstone phenomena during mounting on boards due to their thickness being greater than their width, leading to reliability issues like short-circuits and Manhattan phenomena.
Innovation Solution
A multilayer ceramic component with a hexahedral ceramic body having a thickness-to-width ratio greater than 1, featuring dielectric layers and internal electrodes with specific thickness and stacking configurations, and a mounting board design that ensures the upper surface width is between 0.800 and 0.985 times the lower surface width to prevent toppling and tombstone defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked layers is increased to achieve high capacitance, then the capacitance is improved, but the component becomes more prone to toppling over and tombstone defects during mounting
Solution Approach 1:
The patent applies parameter changes by precisely controlling the thickness of dielectric layers (0.1-0.6 μm) and internal electrodes (0.6 μm or less), and by setting the number of stacked layers to 500 or more. These parameter optimizations enable high capacitance while maintaining mounting reliability by preventing toppling and tombstone defects through balanced structural proportions.
Solution Approach 2:
The patent applies local quality by differentiating the thickness characteristics of different components: dielectric layers are thinned to 0.1-0.6 μm, internal electrodes are controlled to 0.6 μm or less, and the total thickness is increased through stacking 500 or more layers. This localized optimization of thickness parameters in different regions enables high capacitance while maintaining structural stability during mounting.
2Quantity of substance
If the thickness of dielectric layers and internal electrodes is reduced, then the number of stacked layers can be increased, but the manufacturing precision requirements increase
Solution Approach 1:
The patent establishes specific parameter ranges to balance layer count and manufacturing precision: dielectric layer thickness of 0.1-0.6 μm, internal electrode thickness of 0.6 μm or less, and a minimum of 500 stacked layers. These parameter specifications enable high layer counts while maintaining manufacturability by defining clear precision thresholds that prevent excessive complexity.
3Quantity of substance
If the component thickness is made greater than width to achieve high capacitance, then the capacitance is improved, but the component slants during mounting due to surface tension of solder
Solution Approach 1:
The patent achieves high capacitance with T/W>1.0 by stacking 500 or more layers with thinned dielectric layers (0.1-0.6 μm) and internal electrodes (0.6 μm or less), while simultaneously controlling the upper surface width ratio (0.800≦Wa/W≦0.985) to prevent slanting during mounting. This coordinated parameter optimization resolves the conflict between achieving high capacitance through increased thickness and maintaining proper mounting orientation.
Solution Approach 2:
The patent applies asymmetry by controlling the upper surface width (Wa) to be different from the lower surface width (W) with the ratio 0.800≦Wa/W≦0.985. This asymmetric design prevents the component from slanting during mounting by creating a stable geometric configuration that counteracts the tombstone effect caused by solder surface tension, while still achieving T/W>1.0 for high capacitance.
Data Source
AI summary
There are provided a multilayer ceramic electronic component and a mounting board therefor, the multilayer ceramic electronic component including a ceramic body having a hexahedral shape, including dielectric layers, and satisfying T/W>1.0 when a length of the ceramic body is defined as L, a width of a lower surface of the ceramic body is defined as W, and a thickness of the ceramic body is defined as T, and first and second internal electrodes stacked in the ceramic body so as to face each other, having the respective dielectric layers interposed therebetween, wherein when a width of an upper surface of the ceramic body is defined as Wa, 0.800≦Wa/W≦0.985 is satisfied.