Multilayer Ceramic Capacitor Cover Layer Thickness Ratio
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Solution Overview
Problem
Multilayer ceramic capacitors face challenges in achieving high thermal shock resistance and preventing cracks, especially with thin cover layers, as existing solutions reduce capacitance and increase the risk of delamination and cracking.
Innovation Solution
The solution involves forming external electrodes only on the end and at least one principal face, with a thickness relationship between the external electrode and cover layer (Tt ≤ Tc) to minimize thermal stress, and maintaining a cover layer thickness of 10 μm or more but less than 30 μm to increase capacitance and thermal shock resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the thickness of the cover layer is reduced to increase capacitance, then the capacitance increases, but the thermal shock resistance deteriorates and cracks occur
Solution Approach 1:
The patent applies parameter changes by establishing a specific thickness ratio relationship between the external electrode and cover layer (Tt/Tc ≤ 0.8). This parameter optimization allows the cover layer to be thin enough to increase capacitance while maintaining sufficient thermal shock resistance, resolving the contradiction between capacitance enhancement and reliability maintenance.
2Quantity of substance
If the thickness of the dielectric layer is reduced to increase capacitance, then the capacitance increases, but shrinkage strain occurs during sintering leading to delamination and cracking
Solution Approach 1:
The patent applies parameter changes by optimizing the thickness of the dielectric layer to a specific range (0.5 μm to 2.0 μm) and controlling the shrinkage strain within ±5%. This parameter optimization enables the dielectric layer to be thin enough to increase capacitance while maintaining structural integrity during sintering, preventing delamination and cracking.
3Ease of operation
If external electrodes are formed on all five faces to improve connectivity, then the ease of operation improves, but the thermal stress increases and cracks occur
Solution Approach 1:
The patent applies local quality by selectively forming external electrodes on specific faces of the capacitor based on the mounting direction. Instead of uniformly forming electrodes on all five faces, the patent optimizes the electrode configuration for each face, reducing thermal stress while maintaining adequate connectivity for the intended application.
4Quantity of substance
If the continuity of internal electrode is increased to reduce voids, then the capacitance increases, but the shrinkage stress concentrates and causes cracking
Solution Approach 1:
The patent applies parameter changes by optimizing the continuity of the internal electrode to a specific range (0.7 to 0.95) rather than maximizing it to 1.0. This parameter optimization balances the capacitance enhancement from reduced voids with the crack resistance from distributed shrinkage stress, resolving the contradiction between capacitance and strength.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances capacitance while significantly improving thermal shock resistance and suppressing crack generation, ensuring reliable moisture resistance and mounting performance.
Implementation Method 1
Tt representing the thickness of the external electrode and Tc representing the thickness of the cover layer satisfy the relationship of Tt/Tc≤0.8
Data Source
AI summary
A multilayer ceramic capacitor includes an element body of roughly rectangular solid shape which is constituted by dielectric layers alternately stacked with internal electrode layers having different polarities, with a pair of cover layers formed on it to cover the top and bottom faces in the direction of lamination of the foregoing, and which has a pair of principal faces, a pair of end faces, and a pair of side faces, wherein external electrodes are formed on the pair of end faces and at least one of the pair of principal faces of the element body, and Tt representing the thickness of the external electrode and Tc representing the thickness of the cover layer satisfy the relationship of 1/30≤Tt/Tc≤4/5, and the thickness of the cover layers, or Tc, is 10 μm or more but 30 μm or less.