Multilayer Ceramic Capacitor Defect Portion Stress Relief
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Solution Overview
Problem
Existing multilayer ceramic capacitors face issues with cracks and chips in the dielectric ceramic layer due to stress generated during firing, which affects the reliability and performance of the components.
Innovation Solution
The multilayer ceramic capacitor design incorporates a specific configuration with alternating internal electrode layers and dielectric ceramic layers, including a defect portion in the dielectric ceramic layer to absorb stress, and uses different compositions for the dielectric ceramic layers to optimize the structure and prevent cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a dielectric ceramic layer for level difference elimination is included in the multilayer body, then the capacitance and miniaturization are improved, but cracks and chips occur in the dielectric ceramic layer due to stress generated during firing
Solution Approach 1:
The patent applies local quality by creating a defect portion (void or cavity) at a specific location within the dielectric ceramic layer for level difference elimination. This localized structural modification allows the majority of the dielectric ceramic layer to maintain its integrity and mechanical strength, while the defect portion specifically addresses the level difference issue without causing widespread cracks and chips throughout the layer.
Solution Approach 2:
The defect portion is intentionally designed beforehand to absorb and cushion the stress generated during firing. By pre-positioning this defect portion in the dielectric ceramic layer, the patent prepares a stress relief mechanism that prevents the propagation of cracks and chips that would otherwise occur during the firing process, thereby maintaining reliability while achieving the desired capacitance.
2Quantity of substance
If the thickness of the side margin is reduced to increase the area of internal electrode layers, then the capacitance is improved, but the structural integrity and stress resistance are worsened
Solution Approach 1:
The patent maintains adequate side margin thickness in the regions where mechanical strength is critical, while allowing the internal electrode layers to extend closer to the edges in regions where capacitance is prioritized. The defect portion is strategically positioned to provide local stress relief without compromising the overall structural integrity of the side margins.
Solution Approach 2:
The defect portion serves as a pre-positioned stress cushion that compensates for the reduced structural reserve caused by thinner side margins. This allows the design to achieve higher capacitance through increased internal electrode area while the defect portion absorbs the additional stress, preventing catastrophic failure.
3Reliability
If different compositions are used for dielectric ceramic layers to optimize structure, then the reliability is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent uses different compositions for dielectric ceramic layers at different locations within the multilayer body. Specifically, the dielectric ceramic layers containing the defect portion have optimized composition to accommodate the stress relief function, while other dielectric ceramic layers maintain standard composition. This localized compositional differentiation improves reliability without requiring all layers to be manufactured with complex multi-composition specifications.
Solution Approach 2:
The patent segments the dielectric ceramic layers into different functional zones: layers with defect portions that have optimized composition for stress management, and layers without defect portions that use standard composition. This segmentation allows the manufacturing process to handle complexity in a modular fashion, applying different composition requirements only where necessary rather than uniformly across all layers.
Data Source
AI summary
A multilayer ceramic capacitor includes, in at least one of a region between an end of a first internal electrode layer which is not connected to a second external electrode and the second external electrode, and a region between an end of a second internal electrode layer which is not connected to a first external electrode and the first external electrode, in a length direction, a defect portion provided on a plane including a stacking direction and a width direction, such that the defect portion is located between the first dielectric ceramic layers in the stacking direction and is located between the second dielectric ceramic layer and the third dielectric ceramic layer in the width direction.