MLCC Electrode Layout With Dielectric Patterns for Higher BDV

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Solution Overview

Problem

Multilayer ceramic capacitors (MLCCs) face issues due to step portions formed by thickness differences between central and edge portions, leading to bent internal electrodes and reduced breakdown voltage (BDV) characteristics.

Innovation Solution

The MLCC design includes first and second internal electrodes exposed to specific surfaces, with first and second dielectric patterns filling spaces between the electrodes, and lateral insulating layers on the body's surfaces to prevent infiltration of conductive foreign substances.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the stacking number of dielectric layers and internal electrodes is increased to achieve high capacity and compact size, then the capacity and integration are improved, but step portions are formed due to thickness differences, causing internal electrode deformation and reduced reliability

Engineering Contradiction:
ImprovecapacityVSAvoidbreakdown voltage characteristics
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies local quality by forming a margin portion with a different structure from the central portion. Specifically, the margin portion has a reduced stacking number of dielectric layers and internal electrodes, or a different thickness configuration, to prevent step portions from forming at the edges while maintaining high stacking density in the central region for high capacity.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the MLCC body into distinct regions: a central portion with high stacking density for capacity, and a margin portion with reduced stacking or different thickness to prevent edge effects. This segmentation allows each region to optimize its function without compromising the other.

Inventive Principle:
Principle #1Segmentation

2Volume of moving object

If thin-film dielectric layers and internal electrodes are highly stacked to achieve compact size, then the size is reduced, but step portions cause internal electrodes to bend, reducing breakdown voltage characteristics

Engineering Contradiction:
ImprovesizeVSAvoidinternal electrode deformation
Core Design Contradiction:
Volume of moving objectVSManufacturing precision

Solution Approach 1:

The margin portion is designed with local quality differences - either reduced stacking number or adjusted thickness - to compensate for the step portions created by high-density stacking in the central region. This local modification prevents electrode bending at the edges while maintaining compact overall size.

Inventive Principle:
Principle #3Local quality

3Area of stationary object

If the margin width is reduced to remove empty space in the margin portion, then the capacity layers can be elongated, but step portions form causing internal electrode bending and reduced reliability

Engineering Contradiction:
Improvecapacity layer areaVSAvoidbreakdown voltage characteristics
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent creates a margin portion with locally different characteristics (reduced stacking or modified thickness) that serves as a buffer zone. This allows the central capacity layers to be elongated for high capacity while the margin portion absorbs the step portion effects, preventing electrode bending and maintaining reliability.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12334262B2Multilayer ceramic capacitor and board having the same
Publication Date: 2025.06.17 SAMSUNG ELECTRO MECHANICS CO LTD
  • US12334262B2 patent drawing
  • US12334262B2 patent drawing
  • US12334262B2 patent drawing

AI summary

A multilayer ceramic capacitor (MLCC) includes a body including first dielectric layers and second dielectric layers, the body including first to sixth surfaces, a second surface, a third surface, a fourth surface, a fifth surface and a sixth surface; first internal electrodes disposed on the first dielectric layers, exposed to the third surface, the fifth surface, and the sixth surface, and spaced apart from the fourth surface by first spaces; second internal electrodes disposed on the second dielectric layers to oppose the first internal electrodes with the first dielectric layers or the second dielectric layers interposed therebetween, exposed to the fourth surface, the fifth surface, and the sixth surface, and spaced apart from the third surface by second spaces; first dielectric patterns disposed in at least a portion of the first spaces, and second dielectric patterns disposed in at least a portion of the second spaces; and lateral insulating layers.