Multilayer Ceramic Capacitor Electrode Width Ratio for Reliability
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Solution Overview
Problem
The miniaturization of multilayer ceramic electronic components to achieve high capacitance leads to increased reliability issues due to stress-induced short circuits near the cover layer, caused by the increased number of stacked layers and reduced thickness of dielectric and internal electrodes.
Innovation Solution
A multilayer ceramic capacitor design with a ceramic main body having dielectric layers and internal electrodes, where the average thickness and width ratios in different regions are carefully controlled to ensure a high capacitance while maintaining reliability, with specific ratios for the internal electrodes and dielectric layers to prevent short circuits and optimize capacitance formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the thickness of dielectric layers and internal electrodes is reduced to increase the number of stacked layers, then high capacitance is achieved, but reliability is degraded due to increased stress and short circuit frequency near the cover layer
Solution Approach 1:
The patent applies local quality by differentiating the dielectric layer thickness across different regions of the capacitor. The first dielectric layer near the cover layer has a greater thickness than the second dielectric layer in the central region. This local variation optimizes the structure by providing enhanced stress resistance where needed (near the cover layer) while maintaining high capacitance in the central region, thereby resolving the contradiction between achieving high capacitance and maintaining reliability.
2Quantity of substance
If the number of stacked layers is increased to achieve high capacitance, then capacitance is improved, but the influence of step portions increases causing reliability degradation
Solution Approach 1:
The patent implements local quality by varying the dielectric layer thickness in different regions. The first dielectric layer has a greater thickness than the second dielectric layer, creating a graduated structure that reduces step portions. This local differentiation allows the patent to maintain manufacturing precision while increasing the number of stacked layers for high capacitance, thus resolving the contradiction between capacitance improvement and step portion control.
3Quantity of substance
If dielectric layers are thinned to increase stacked layers, then high capacitance is realized, but stress-induced short circuits increase near the cover layer
Solution Approach 1:
The patent applies local quality by creating region-specific dielectric layer thicknesses. The first dielectric layer near the cover layer has a greater thickness to provide stress resistance and prevent short circuits in that region, while the second dielectric layer in the central region has a thinner thickness to maximize capacitance. This localized differentiation resolves the contradiction between achieving high capacitance and preventing stress-induced short circuits.
Solution Approach 2:
The patent employs beforehand cushioning by designing the first dielectric layer with greater thickness before the pressing process. This thicker layer acts as a cushion that absorbs and distributes stress during the pressing operation, preventing stress-induced short circuits near the cover layer before they can occur. This proactive design resolves the contradiction between high capacitance and stress resistance.
Data Source
AI summary
A multilayer ceramic electronic component includes a ceramic main body including dielectric layers and satisfying T/W>1.0 when W and T are width and thickness, respectively; and first and second internal electrodes stacked in the ceramic main body and facing each other with the dielectric layer interposed therebetween, the ceramic main body including an active layer corresponding to a capacitance forming portion contributing to capacitance formation and a cover layer corresponding to a non-capacitance forming portion provided on at least one of uppermost and lowermost surfaces of the active layer, and when the active layer is divided into three regions in a direction in which the first and second internal electrodes are stacked, an average width of internal electrodes in a central region of the three regions is Wa, and an average width of internal electrodes in upper and lower regions of the three regions is Wb, 0.920≦Wb/Wa≦0.998 is satisfied.