Multilayer Ceramic Capacitor ESR Adjustment via Localized Electrode Materials
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Solution Overview
Problem
Multilayer ceramic capacitors face challenges in achieving balanced ESR and ESL characteristics, leading to voltage noise issues in power supplies, particularly in high-frequency applications, and limited mounting space in compact electronic devices.
Innovation Solution
A multilayer ceramic capacitor design with a ceramic body having dielectric layers, alternating internal electrodes, and strategically positioned external electrodes to adjust ESR characteristics, while maintaining low ESL, is implemented. The ESR adjustment region is integrated with additional internal electrodes, and external electrodes are placed on one surface to reduce inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external and internal electrodes are formed of materials having high electrical resistance to adjust ESR characteristics, then ESR characteristics are improved, but current concentration phenomenon occurs due to pin hole phenomenon causing localized heat spots
Solution Approach 1:
The patent applies different materials with different electrical resistance characteristics to different regions of the electrodes. Specifically, it uses a first electrode material with higher electrical resistance in regions prone to current concentration and pinhole formation, while using a second electrode material with lower electrical resistance in other regions. This local differentiation allows the capacitor to achieve desired ESR characteristics while avoiding current concentration phenomena and localized heat spots.
2Speed
If operating frequency of the multilayer ceramic capacitor is increased to improve decoupling performance, then decoupling capability is improved, but lower equivalent series inductance (ESL) value is required
Solution Approach 1:
The patent transitions from conventional planar electrode arrangements to a three-dimensional stacked electrode configuration. By stacking multiple electrode layers in the thickness direction of the ceramic body, the current path length is reduced and the inductance is minimized. This dimensional change enables the capacitor to achieve low ESL values necessary for high-frequency decoupling applications while maintaining adequate capacitance.
3Area of moving object
If area of the circuit board is reduced to accommodate compact electronic devices, then device size is reduced, but mounting space of decoupling capacitor is limited
Solution Approach 1:
The patent employs a compact stacked multilayer structure where multiple functional layers (dielectric layers and electrode layers) are nested within each other in the thickness direction. This nesting approach allows the capacitor to achieve adequate capacitance and ESR characteristics in a small footprint, enabling mounting in compact electronic devices with limited circuit board area.
Data Source
AI summary
A multilayer ceramic capacitor includes a ceramic body having a plurality of dielectric layers layered in a width direction of the ceramic body, and including an active region including first and second internal electrodes alternately disposed with at least one of the dielectric layers interposed therebetween and an ESR adjustment region including one or more third internal electrodes; and first, second and third external electrodes disposed on a mounting surface of the ceramic body to be spaced apart from each other in a length direction of the ceramic body, and a board having the same.