Multilayer Ceramic Capacitor with Gradient Crystal Grain Structure
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Solution Overview
Problem
Multilayer ceramic capacitors face challenges in downsizing while maintaining capacity and reliability, as reducing cover sheet thickness can lead to thermal shock cracks and increased Equivalent Series Resistance (ESR) due to weaker cover sheet strength and larger crystal grains in internal electrode layers.
Innovation Solution
A multilayer ceramic capacitor design with surface portions and a center portion, where the average length of crystal grains in the surface portions is 0.8 times or less than in the center portions, enhancing crystal grain boundaries for strength and reducing ESR, achieved through specific manufacturing methods involving ceramic and metal paste processing and baking conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the thickness of the cover sheets is reduced to downsize the capacitor and enlarge capacity region, then the volume of capacity region is enlarged, but the strength of cover sheets becomes small leading to thermal shock cracks and reduced reliability
Solution Approach 1:
The patent applies local quality by creating a gradient in crystal grain size within the internal electrode layers. Surface portions have finer crystal grains (0.8 times or less than center portions) to provide strength where thermal shock occurs, while center portions have larger grains to maintain low ESR. This spatial variation in microstructure allows the thin cover sheets to be used without compromising reliability.
2Length of moving object
If the thickness of the cover sheets is reduced, then downsizing is achieved, but thermal shock cracks may occur due to insufficient cover sheet strength
Solution Approach 1:
The patent makes the internal electrode layers stronger at the surface portions through fine crystal grain structure, which compensates for the reduced cover sheet strength. The fine grains at the surface create more grain boundaries that act as barriers to crack propagation, effectively reinforcing the regions most susceptible to thermal shock.
Solution Approach 2:
The manufacturing method applies preliminary action by controlling the filling condition during compression molding before baking. By adjusting the filling condition, the patent pre-establishes the crystal grain size distribution pattern (finer at surfaces, coarser at center) that will prevent thermal shock cracks during subsequent thermal cycling.
3Reliability
If crystal grains of the internal electrode layer are made finer and the number of crystal grains is enlarged, then reliability is improved, but the ESR becomes large
Solution Approach 1:
The patent resolves this contradiction by applying different crystal grain sizes to different regions. Surface portions have fine crystal grains to improve reliability and resistance to thermal shock, while center portions have larger crystal grains to maintain low ESR. This spatial differentiation allows both requirements to be satisfied simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves thermal shock resistance and maintains reliability by increasing the number of crystal grain boundaries in surface portions while suppressing ESR, even with reduced cover sheet thickness.
Implementation Method 1
a third step of providing cover sheets including main component ceramic powders on an upper face and a lower face of a ceramic multilayer structure in a stacking direction of the ceramic multilayer structure obtained by the second step, and compressing the cover sheets toward the upper face and the lower face
Implementation Method 2
a fourth step of forming a multilayer structure in which each of dielectric layers and each of internal electrode layers are alternately stacked, by baking the ceramic multilayer structure obtained by the third step
Data Source
AI summary
A multilayer ceramic capacitor includes: a multilayer structure in which each of dielectric layers and each of internal electrode layers are alternately stacked, a main component of the dielectric layers being ceramic, wherein: the multilayer structure comprises surface portions and a center portion in a stacking direction of the dielectric layers and the internal electrode layers, the surface portions having a first thickness from a surface of the multilayer structure, the center portion being next to the surface portion in the stacking direction and having a second thickness; and an average length of crystal grains of a main component metal of the internal electrode layers of the surface portions is 0.8 times or less than an average length of crystal grains of a main component metal of the internal electrode layers of the center portion.