MLCC Dielectric Grain Distribution for DC-Bias and Permittivity
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Solution Overview
Problem
High-capacitance multilayer ceramic capacitors face challenges in maintaining high permittivity while ensuring excellent DC-bias characteristics, as reducing grain size to prevent short-circuit defects can lead to deteriorated DC-bias characteristics, and increasing grain size to enhance permittivity may compromise capacitance.
Innovation Solution
A multilayer ceramic capacitor design with dielectric grains sized between 50 nm and 450 nm, distributed in sections within a 0.025 to 0.20 fraction, and a dielectric layer thickness of 0.8 μm or less, using a dielectric ceramic composition that includes a base material of BaTiO3 and accessory ingredients to achieve high permittivity and improved DC-bias characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If grain size is decreased to prevent short-circuit defects, then reliability is improved, but permittivity deteriorates
Solution Approach 1:
The patent applies parameter changes by precisely controlling grain size distribution within a specific range (50-450 nm) and optimizing the fraction of grains in each size section. This controlled parameter adjustment allows the dielectric layer to maintain high permittivity while preventing short-circuit defects through appropriate grain size selection.
Solution Approach 2:
The patent uses composite materials by combining BaTiO3 base material with accessory ingredients to create a dielectric ceramic composition that achieves both high permittivity and reliability. The composite nature of the material allows optimization of multiple properties simultaneously through careful selection of constituent materials and their ratios.
2Stability of the object's composition
If grain size is increased to enhance permittivity, then capacitance is improved, but DC-bias characteristics deteriorate
Solution Approach 1:
The patent resolves this contradiction by changing the grain size distribution parameters, specifically limiting grains to a maximum of 450 nm and establishing a fractional distribution across size sections. This parameter optimization ensures high permittivity is achieved without exceeding the grain size threshold that would degrade DC-bias characteristics.
Solution Approach 2:
The patent applies local quality by creating different grain size distributions in different sections of the dielectric layer. By controlling the fraction of grains in each size section (50-100 nm, 100-150 nm, etc.), the patent achieves local optimization where smaller grains maintain DC-bias characteristics while larger grains contribute to permittivity.
3Productivity
If dielectric layer thickness is reduced to achieve high capacitance, then productivity is improved, but short-circuit defects increase
Solution Approach 1:
The patent changes the parameter of grain size distribution within the thin dielectric layer (thickness ≤ 0.8 μm) to prevent short-circuit defects. By optimizing grain size to 50-450 nm with controlled fractional distribution, the patent maintains high capacitance density in the thin layer while ensuring reliability through appropriate grain size selection that prevents defect formation.
Solution Approach 2:
The patent employs composite dielectric ceramic composition with BaTiO3 and accessory ingredients to achieve both thin layer compatibility and defect resistance. The composite material structure allows the thin dielectric layer to maintain structural integrity and electrical performance despite reduced thickness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high nominal and effective permittivity, high-temperature withstand voltage, and a temperature coefficient of capacitance within ±15% at 85°C, while maintaining high capacitance and reliability under DC-bias conditions.
Implementation Method 1
a fraction of the dielectric grains in each of the sections within a range of 50 nm to 450 nm is within a range of 0.025 to 0.20... high nominal and effective permittivity
Data Source
AI summary
A multilayer ceramic capacitor includes: a ceramic body in which dielectric layers and first and second internal electrodes are alternately stacked; and first and second external electrodes formed on an outer surface of the ceramic body and electrically connected to the first and second internal electrodes, respectively. In a microstructure of the dielectric layer, dielectric grains are divided by a dielectric grain size into sections each having an interval of 50 nm, respectively, a fraction of the dielectric grains in each of the sections within a range of 50 nm to 450 nm is within a range of 0.025 to 0.20, and a thickness of the dielectric layer is 0.8 μm or less.