Multilayer Chip Capacitor Reducing ESL via Intermediary Ground Electrodes
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Solution Overview
Problem
Multilayer chip capacitors face challenges in reducing equivalent series inductance (ESL) while maintaining process reliability and preventing short-circuits between outer electrodes of opposite polarity, especially in high-current, high-frequency electronic devices.
Innovation Solution
The design incorporates third inner electrodes with conductive patterns matching the leads of first and second inner electrodes, which are connected to outer electrodes, ensuring a sufficient active region width for electroless plating and preventing capacitance formation, thus enhancing process reliability and reducing ESL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the pitch between outer electrodes is reduced to lower ESL, then the equivalent series inductance decreases, but the possibility of short-circuit between outer electrodes of opposite polarity increases
Solution Approach 1:
The patent introduces a ground electrode as an intermediary element positioned between the outer electrodes of opposite polarity. This ground electrode acts as a mediator that prevents direct contact and potential short-circuits between the positive and negative outer electrodes, while still allowing the pitch between outer electrodes to be reduced for lower ESL.
Solution Approach 2:
The patent adds a vertical dimension to the electrode arrangement by stacking ground electrodes between the outer electrodes in the thickness direction. This dimensional approach allows the outer electrodes to be positioned closer together in the planar direction (reducing pitch and ESL) while maintaining separation through the vertical stacking of ground electrodes.
2Reliability
If the pitch between outer electrodes is reduced to lower ESL, then the equivalent series inductance decreases, but the manufacturing precision requirements increase due to electroless plating process constraints
Solution Approach 1:
The patent forms the ground electrode patterns on the inner electrodes before applying the outer electrodes through electroless plating. This preliminary action establishes precise reference positions for the outer electrodes, ensuring that even when pitch is reduced, the electroless plating process can accurately deposit outer electrodes at the correct locations without short-circuits.
Solution Approach 2:
The ground electrodes serve as intermediary reference structures that facilitate the electroless plating process. By having ground electrode patterns预先 formed on the inner electrodes, the plating process can use these as guides to achieve precise pitch control for the outer electrodes.
3Manufacturing precision
If the active region width is increased to ensure sufficient space for electroless plating, then the manufacturing precision improves, but the device volume increases
Solution Approach 1:
The patent utilizes the thickness dimension by stacking ground electrodes vertically between the outer electrodes. This allows the active region width in the planar direction to be minimized for compact size, while still providing sufficient space for electroless plating by extending the structure in the vertical dimension.
Solution Approach 2:
The patent nests the ground electrodes within the structure formed by the outer electrodes and inner electrodes. The ground electrodes are positioned in the space between the outer electrodes, effectively utilizing the available volume without increasing the overall capacitor dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for precise control of outer electrode pitch, reducing ESL and preventing short-circuits, effectively suppressing voltage noise in high-frequency applications.
Implementation Method 1
Outer electrodes may be applied using electroless plating, which allows a pitch between the outer electrodes to be controlled with high precision.
Data Source
AI summary
There are provided a multilayer chip capacitor and a circuit board device. The multilayer chip capacitor includes a capacitor body including a plurality of dielectric layers that are stacked, first and second outer electrodes formed on an outer surface of the capacitor body and having opposite polarity, first and second inner electrodes opposing each other, interleaved with the dielectric layers in the capacitor body, and each including an electrode plate forming capacitance and a lead extending from the electrode plate, the lead of the first inner electrode and the lead of the second electrode being respectively connected to the first and second outer electrodes, and third inner electrodes interposed between the first and second inner electrodes. At least one of the third inner electrodes adjacent to the first inner electrode includes a conductive pattern having the same shape as the lead of the first inner electrode and is connected to the first outer electrode. At least one of the third inner electrodes adjacent to the second inner electrode includes a conductive pattern having the same shape as the lead of the second inner electrode and is connected to the second outer electrode.