Multilayer Ceramic Capacitor Hole Diameter Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing multilayer ceramic capacitors face challenges in preventing electric field concentration, especially when used with high voltages, which can lead to dielectric breakdown.
Innovation Solution
The capacitors incorporate a multilayer body with dielectric layers and internal electrode layers, where the internal electrode layers have holes with varying area equivalent diameters. The thickness of the dielectric layers and the area equivalent diameter of the holes are optimized such that the cumulative distribution of hole diameters at 99% (D99) is less than a specific exponential function of the dielectric layer thickness, ensuring reduced electric field concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the distance between internal electrode layers is increased, then breakdown voltage is improved, but capacitance is reduced
Solution Approach 1:
The patent applies parameter changes by precisely controlling the dielectric layer thickness (0.3 μm to 1.0 μm) and the area equivalent diameter of holes (D99 less than 0.048/t mm) to optimize the balance between breakdown voltage and capacitance. This quantitative parameter optimization resolves the contradiction by finding the optimal range where both requirements are satisfied.
2Quantity of substance
If dielectric layer thickness is reduced, then capacitance is improved, but electric field concentration increases leading to breakdown
Solution Approach 1:
The patent applies local quality by creating holes with specific area equivalent diameters in the internal electrode layers. These holes are strategically positioned and sized (D99 less than 0.048/t mm) to locally modify the electric field distribution, preventing concentration at critical points while maintaining thin dielectric layers for high capacitance.
Solution Approach 2:
The patent uses parameter changes by establishing a specific relationship between dielectric thickness (t) and hole area equivalent diameter (D99 < 0.048/t mm). This mathematical relationship optimizes the local structure to prevent electric field concentration while maintaining thin dielectric layers, resolving the contradiction between capacitance and reliability.
3Reliability
If auxiliary electrodes are added to prevent electric field concentration, then breakdown voltage is improved, but device complexity increases
Solution Approach 1:
The patent applies the taking out principle by removing material (creating holes) from the internal electrode layers instead of adding auxiliary electrodes. This extraction approach prevents electric field concentration by eliminating the problematic continuous electrode structure, simplifying the overall device complexity while achieving the same reliability improvement.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Provided are multilayer ceramic capacitors that are each able to reduce or prevent electric field concentration. A multilayer ceramic capacitor 1 includes a multilayer body 10 including a plurality of dielectric layers 20 that are laminated and a plurality of internal electrode layers 30 that are each laminated on a corresponding one of the plurality of dielectric layers 20, and a first external electrode 40A and a second external electrode 40B. The plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 each electrically connected to the first external electrode 40A and a plurality of second internal electrode layers 32 each electrically connected to the second external electrode40B. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 each include the plurality of holes H having different area equivalent diameters. When an area equivalent diameter at which a cumulative value in a cumulative distribution of the area equivalent diameters of the plurality of holes H is 99% is defined as the area equivalent diameter D99, and the thickness t of each of the plurality of dielectric layers 20 sandwiched between a corresponding one of the plurality of first internal electrode layers 31 and a corresponding one of the plurality of second internal electrode layers 32 is defined as the thickness t, the thickness t of each of the plurality of dielectric layers 20 is 0.5 µm or more and the following formula (1): (area equivalent diameter D99) < 0.0879 × exp (2.86 × t) is satisfied.