Multilayer Ceramic Capacitor Structure for Layer Peeling Prevention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Layer peeling occurs in multilayer ceramic capacitors due to differences in shrinkage behavior between dielectric and internal electrode layers during firing, leading to reduced adhesive force at the interface and potential peeling between layers.
Innovation Solution
Incorporation of a multilayer ceramic capacitor design with silicon oxide segregation regions and a specific cross-sectional area relationship between outer layer interior, chip middle, and outermost effective layer vicinity portions, along with a configuration of external electrodes and internal electrode layers to enhance structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional firing process is used, then manufacturing simplicity is maintained, but layer peeling occurs due to shrinkage difference between dielectric and internal electrode layers
Solution Approach 1:
The patent applies local quality by creating a specific silicon oxide concentration distribution within the dielectric layer. The silicon oxide concentration is higher near the interface with the internal electrode layer compared to other regions, which locally modifies the shrinkage characteristics at the critical interface zone. This local compositional adjustment reduces shrinkage difference and prevents layer peeling without changing the overall manufacturing process.
Solution Approach 2:
The patent changes the chemical composition parameter of the dielectric layer by controlling silicon oxide concentration distribution. Specifically, the silicon oxide concentration is optimized to be 5-20 wt% near the internal electrode layer interface, which alters the thermal and shrinkage properties of the dielectric material in that region, thereby reducing adhesion problems during firing.
2Reliability
If silicon oxide concentration is increased uniformly throughout the dielectric layer, then layer adhesion improves, but dielectric performance deteriorates
Solution Approach 1:
The patent avoids uniform silicon oxide distribution by concentrating silicon oxide specifically near the internal electrode layer interface (5-20 wt%) while maintaining lower concentrations in other dielectric regions. This localized approach ensures adhesion improvement at the critical interface without compromising the overall dielectric performance of the capacitor.
Solution Approach 2:
The dielectric layer is functionally segmented into different zones with different silicon oxide concentrations: a high-concentration zone (5-20 wt%) at the interface with internal electrodes for adhesion, and lower-concentration zones in the bulk dielectric for maintaining electrical performance. This segmentation allows each zone to optimize its function independently.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces or prevents layer peeling, ensuring reliable adhesion and durability of the capacitor layers.
Implementation Method 1
a plurality of silicon oxide segregation regions, and in a cross section of the multilayer body in a plane parallel or substantially parallel to the width direction and the height direction, a relationship of average cross sectional areas of a plurality of silicon oxide segregation regions in respective portions
Data Source
AI summary
A multilayer ceramic capacitor includes a multilayer body including an outer layer interior portion, an outermost effective layer vicinity portion, a chip middle portion, and silicon oxide segregation regions. In a cross section of the multilayer body in a plane parallel or substantially parallel to a width direction and a height direction, a relationship of average cross section areas of the silicon oxide segregation regions in the respective portions is expressed as:the outer layer interior portion<the chip middle portion<the outermost effective layer vicinity portion.