Multilayer Ceramic Capacitor Margin Grain Control
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Solution Overview
Problem
Existing multilayer ceramic capacitors face limitations in increasing capacitance due to difficulties in reducing the margin part region of dielectric layers and maintaining moisture-resistance characteristics, with current methods either compromising capacitance or vulnerability to impacts.
Innovation Solution
A multilayer ceramic capacitor design with specific grain size control for dielectric grains in margin and effective layers, where Gw < Gt < Ga, and a method of manufacturing involving ceramic slurry application to form margin parts with an average thickness of 18 μm or less, enhancing the overlap area of internal electrodes and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the margin part region of the dielectric layer is reduced to increase internal electrode overlap area, then capacitance increases, but moisture-resistance characteristics deteriorate and the structure becomes vulnerable to impacts
Solution Approach 1:
The patent applies local quality by forming a cover layer with different material composition and grain size characteristics specifically on the margin parts of the dielectric layer. This cover layer has finer grain size and different sintering properties compared to the main dielectric layer, creating localized enhanced protection against moisture penetration and mechanical impacts while preserving the overall capacitance-enhancing margin reduction.
Solution Approach 2:
The patent uses composite materials by combining the main dielectric layer with a cover layer having different compositional characteristics. The cover layer contains specific ceramic powders with controlled grain sizes that differ from the main dielectric, creating a composite structure that provides both capacitance functionality and enhanced environmental resistance in the margin regions.
2Quantity of substance
If the margin part thickness is reduced to increase internal electrode overlap area, then capacitance increases, but carbon removal during calcining and sintering becomes difficult
Solution Approach 1:
The patent applies local quality by creating a cover layer with specific compositional characteristics on the margin parts that facilitates carbon removal during sintering. The cover layer's unique material properties, including controlled grain size and composition, enable effective carbon elimination in the margin regions even when the overall margin thickness is reduced to maximize electrode overlap.
3Volume of moving object
If the multilayer ceramic capacitor is miniaturized to meet electronic product size requirements, then device size decreases, but the overlap area of internal electrodes is limited
Solution Approach 1:
The patent applies dimensionality change by utilizing the vertical dimension through multi-layer stacking to compensate for the reduced horizontal overlap area caused by miniaturization. By increasing the number of dielectric layers and internal electrodes in the vertical direction, the total capacitance is maintained or enhanced despite the reduced device footprint in planar dimensions.
Solution Approach 2:
The patent applies local quality by optimizing the margin part dimensions and cover layer characteristics in specific regions to maximize the usable overlap area of internal electrodes within the constrained miniaturized form factor, thereby achieving high capacitance in a small volume.
Data Source
AI summary
There is provided a multilayer ceramic capacitor including a ceramic body having first and second side surfaces facing each other, and third and fourth end surfaces connecting the first and second side surfaces, a plurality of internal electrodes formed in the ceramic body and having one ends thereof exposed to the third end surface or the fourth end surface, and a first side margin part and a second side margin part formed such that an average thickness thereof from the first and second side surfaces to edges of the internal electrodes is 18 μm or less.