Multilayer Ceramic Capacitor with Localized Molybdenum Doping
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Solution Overview
Problem
The reliability of multilayer ceramic capacitors is compromised due to structural defects caused by high concentrations of donor elements in the end margin and side margin regions, leading to abnormal grain growth and delayed sintering, which can result in reduced lifetime and humidity resistance.
Innovation Solution
A multilayer ceramic capacitor design with a lower concentration of donor elements in the cover layer, end margin region, and side margin region compared to the dielectric layers, and a manufacturing method involving specific patterns of metal conductive pastes and ceramic particles to alternately stack the layers, ensuring the donor element concentration is controlled to prevent structural defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the thickness of the dielectric layer is reduced to downsize the capacitor, then the chip size is reduced, but the voltage applied to each dielectric layer increases and the lifetime is shortened
Solution Approach 1:
The patent applies local quality by adding donor elements (such as Mo, Nb, Ta, or W) specifically to the dielectric layer to enhance its electrical properties and lifetime. This localized modification allows the dielectric layer to withstand higher voltages without compromising the overall miniaturization of the capacitor.
Solution Approach 2:
The patent changes the chemical composition parameters of the dielectric layer by introducing donor elements. This parameter change increases the electrical breakdown strength and lifetime of the dielectric layer, enabling it to function reliably at reduced thickness while maintaining the capacitor's downsized form factor.
2Reliability
If a high concentration of donor element is added to the dielectric layer to improve electrical properties, then the electrical performance is enhanced, but structural defects occur due to delayed sintering or abnormal grain growth at chip surface
Solution Approach 1:
The patent applies local quality by creating a non-uniform distribution of donor elements within the dielectric layer. The concentration of donor elements is higher in the bulk dielectric layer to improve electrical properties, but lower at the chip surface and margin regions to prevent abnormal grain growth and structural defects. This spatially varying composition allows simultaneous achievement of enhanced electrical performance and structural integrity.
Solution Approach 2:
The patent applies partial action by adding donor elements only to the extent necessary for improving electrical properties, while deliberately limiting the concentration in regions where it would cause harm. The donor element concentration is optimized to be sufficient for electrical performance enhancement in the bulk, but restricted at the surface to avoid structural defects.
3Volume of moving object
If the thickness of the dielectric layer is reduced to downsize the capacitor, then the chip size is reduced, but the reliability is degraded
Solution Approach 1:
The patent applies local quality by modifying the composition of the dielectric layer with donor elements to enhance its reliability. This localized compositional change allows the thinner dielectric layer to withstand higher electric fields and maintain reliability, enabling capacitor downsizing without sacrificing reliability.
Solution Approach 2:
The patent changes the chemical composition parameters of the dielectric layer by introducing donor elements, which increases the electrical breakdown strength and reliability. This parameter change enables the dielectric layer to function reliably at reduced thickness,从而实现 capacitor miniaturization while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and humidity resistance of the multilayer ceramic capacitors by suppressing abnormal grain growth and delayed sintering, thereby improving the lifetime and breakdown voltage.
Implementation Method 1
a structural defect may occur because of delay of sintering or abnormal grain growth at a chip surface
Data Source
AI summary
A multilayer ceramic capacitor includes: a multilayer structure in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked, the plurality of internal electrode layers being alternately exposed to a first edge face and a second edge face of the multilayer structure, wherein: a concentration of Mo with respect to a main component ceramic of an end margin region and a side margin region is lower than a concentration of Mo with respect to a main component ceramic of the dielectric layers in the multilayer structure.