Multilayer Ceramic Capacitor Multiple Resonance Design
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Solution Overview
Problem
Existing multilayer ceramic capacitors struggle to achieve multiple resonance frequencies, which limits their ability to effectively reduce noise components across various frequencies, as the specific parameter ranges for achieving these frequencies are not disclosed in prior art, making it difficult to manufacture capacitors capable of suppressing multiple noise frequencies.
Innovation Solution
A ceramic electronic device with a multilayer chip structure featuring alternating internal electrode and dielectric layers, where specific capacity and inductance ratios (C1·L1)/(C2·L2) are optimized to be less than 0.5 or greater than 1.9, allowing for the generation of multiple resonance frequencies, thereby enhancing noise suppression capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single multilayer ceramic capacitor is used with conventional design, then the structure is simple and manufacturing is easy, but only a single resonance frequency can be achieved which limits noise suppression capability
Solution Approach 1:
The multilayer ceramic capacitor is divided into multiple capacity regions (first capacity region with capacitance C1 and second capacity region with capacitance C2) within a single chip structure. Each region has different capacitance values and inductance characteristics, enabling the generation of multiple resonance frequencies. This segmentation allows the capacitor to suppress multiple noise frequency components simultaneously while maintaining a relatively compact single-device form factor.
Solution Approach 2:
Different regions of the capacitor chip are designed with locally optimized properties - the first capacity region has specific capacitance C1 and inductance L1, while the second capacity region has different capacitance C2 and inductance L2. The ratio relationship (C1·L1)/(C2·L2) ≥ 0.5 is maintained to ensure proper resonance frequency separation. This local differentiation enables each region to contribute to noise suppression at different frequency ranges.
2Adaptability or versatility
If multiple capacity regions with different parameters are created, then multiple resonance frequencies can be achieved, but manufacturing precision requirements increase
Solution Approach 1:
The invention specifies parameter ranges and relationships to achieve the desired functionality - the ratio (C1·L1)/(C2·L2) should be ≥ 0.5. By defining this relationship constraint rather than requiring absolute precision for each individual parameter, the design allows for manufacturing variability while still ensuring multiple resonance frequencies are generated. The capacitance values C1 and C2 and inductance values L1 and L2 can vary within acceptable ranges as long as the ratio relationship is maintained.
3Reliability
If conventional single-capacitance design is used, then manufacturing is straightforward, but the decoupling effect is limited to a single frequency
Solution Approach 1:
The multilayer ceramic capacitor is designed to perform multiple functions simultaneously - it provides decoupling effect at multiple resonance frequencies (first resonance frequency from C1-L1 and second resonance frequency from C2-L2). This multi-functionality allows a single capacitor device to replace what would traditionally require multiple separate capacitors or additional noise suppression components, improving reliability while managing complexity through integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The optimized multilayer ceramic capacitors can absorb noise at multiple frequencies, effectively reducing noise components by achieving two or more resonance frequencies depending on the capacity and inductance ratio, improving noise suppression performance.
Implementation Method 1
each of internal electrode layers 12 and each of dielectric layers 11 are alternately stacked
Implementation Method 2
first capacity region 10a having a first electrostatic capacity C1
Implementation Method 3
first capacity region 10a having a first electrostatic capacity C1 and a first inductance L1
Implementation Method 4
the first electrostatic capacity C1, the first inductance L1, the second electrostatic capacity C2 and the second inductance L2 satisfy (C1·L1)/(C2·L2)≥0.5
Data Source
AI summary
A ceramic electronic device includes: a multilayer chip in which each of internal electrode layers and each of dielectric layers are alternately stacked, wherein the multilayer chip has a first capacity region having a first electrostatic capacity C1 and a first inductance L1 and a second capacity region having a second electrostatic capacity C2 and a second inductance L2, wherein the first electrostatic capacity C1, the first inductance L1, the second electrostatic capacity C2 and the second inductance L2 satisfy (C1·L1)/(C2·L2)<0.5 or 1.9<(C1·L1)/(C2·L2).