Multilayer Ceramic Capacitor Noise Reduction via Relative Displacement Index

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Solution Overview

Problem

Multilayer capacitors generate acoustic noise due to piezoelectric vibrations, which cause discomfort, and they also suffer from warpage issues that affect their reliability and performance.

Innovation Solution

A multilayer capacitor design with a specific configuration including dielectric layers, internal and external electrodes, conductive resin layers, and an insulator with a relative displacement index between 0.003 and 0.055, which reduces acoustic noise and enhances warpage strength by optimizing the structural parameters and materials used.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If a multilayer capacitor uses a conventional structure without optimized geometric parameters, then manufacturing is simpler, but acoustic noise increases and warpage strength decreases

Engineering Contradiction:
Improveacoustic noiseVSAvoidstructural parameter optimization
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by optimizing the relative displacement index using specific geometric parameters (La, Lm, Ta, Tc, Te) that satisfy a mathematical relationship. This optimization reduces piezoelectric vibrations and acoustic noise while maintaining manufacturing feasibility through defined parameter ranges.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements preliminary action by pre-calculating and pre-defining the optimal geometric parameters and their relationships before manufacturing. The relative displacement index formula allows manufacturers to design capacitors with noise-reducing dimensions from the outset, rather than requiring post-manufacturing adjustments.

Inventive Principle:
Principle #10Preliminary action

2Object-affected harmful factors

If the insulator thickness is increased to reduce acoustic noise, then noise reduction improves, but manufacturing complexity and cost increase

Engineering Contradiction:
Improveacoustic noise reductionVSAvoidinsulator thickness specification
Core Design Contradiction:
Object-affected harmful factorsVSEase of manufacture

Solution Approach 1:

The patent specifies that the insulator thickness Te should be 16 μm or greater to achieve effective noise reduction. This parameter change provides a clear manufacturing guideline that balances noise reduction performance with manufacturing capability, avoiding excessively thick insulators that would complicate production.

Inventive Principle:
Principle #35Parameter changes

3Object-affected harmful factors

If the capacitor body dimensions are optimized for noise reduction, then acoustic noise decreases, but warpage strength may be affected

Engineering Contradiction:
Improveacoustic noiseVSAvoidwarpage strength
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The patent optimizes the relative displacement index using the formula involving La, Lm, Ta, Tc, and Te parameters. This mathematical relationship ensures that dimensional changes for noise reduction are coordinated with structural integrity requirements, maintaining warpage strength while reducing acoustic noise.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent uses composite materials including the insulator layer (16 μm or greater thickness) in combination with the capacitor body structure. This composite approach enhances both noise reduction and structural stability, preventing warpage while achieving acoustic noise suppression.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces acoustic noise by 7 dB or more and improves warpage strength, ensuring the capacitor's stability and performance, particularly when the insulator thickness is 16 μm or greater.

Implementation Method 1

Since the dielectric layer has piezoelectricity using a ferroelectric material, a piezoelectric phenomenon occurs between internal electrodes when a direct or alternating voltage is applied to the multilayer capacitor

Methodology Applied
Scientific EffectPiezoelectricity: Piezoelectric Effect

Data Source

PatentUS11562858B2Multilayer ceramic capacitor and board having the same mounted thereon
Publication Date: 2023.01.24 SAMSUNG ELECTRO MECHANICS CO LTD
  • US11562858B2 patent drawing
  • US11562858B2 patent drawing
  • US11562858B2 patent drawing

AI summary

A multilayer capacitor includes a capacitor body including a dielectric layer and first and second internal electrodes; first and second external electrodes; and an insulator disposed on a first surface of the capacitor body. The capacitor body includes an active region in which first and second internal electrodes overlap each other in a first direction, and upper and lower covers disposed above and below the active region in the first direction. A length of the active region in the second direction is defined as ‘La’, a length of one margin of the capacitor body in the second direction is defined as ‘Lm’, a height of the active region in the first direction is defined as ‘Ta’, a thickness of the lower cover of the capacitor body is defined as ‘Tc’, and a thickness of the insulator is defined as ‘Te’. A relative displacement index, ((La/Lm)−(Ta/Tc))/Te)2, ranges from 0.003 to 0.055.