Multilayer Ceramic Capacitor with Vertical Electrodes for Low ESL
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Solution Overview
Problem
Existing decoupling capacitors face challenges in reducing inductance, leading to unacceptable voltage spikes in high-speed electronic circuits, as conventional designs fail to minimize equivalent series inductance (ESL) effectively.
Innovation Solution
The design incorporates vertically oriented electrodes and closely spaced termination gaps to minimize the current loop area and span, reducing ESL and equivalent series resistance (ESR) through specific electrode configurations and termination techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional capacitor designs are used, then manufacturing is simple, but inductance is high causing voltage spikes
Solution Approach 1:
The patent inverts the conventional electrode arrangement by placing electrodes on the short sides of the capacitor instead of the long sides. This reverse geometry termination fundamentally changes the current path, reducing the loop area and thereby minimizing inductance and voltage spikes in high-speed circuits
Solution Approach 2:
The patent extends electrodes vertically from the mounting surface into the capacitor body, creating a three-dimensional electrode structure. This vertical dimension reduces the horizontal span of current loops, effectively minimizing inductance while maintaining a compact footprint
2Object-affected harmful factors
If electrode span is reduced to minimize inductance, then ESL decreases, but current path length increases
Solution Approach 1:
By inverting the electrode termination geometry to short-side mounting, the patent reduces the horizontal span of current loops. Although vertical electrode extension increases path length, the dramatic reduction in loop area dominates, achieving lower ESL through optimized current cancellation patterns
3Object-affected harmful factors
If termination surface area is increased to reduce resistance, then ESR decreases, but device footprint increases
Solution Approach 1:
The patent utilizes the vertical dimension by extending electrodes upward from the mounting surface. This provides additional termination surface area for reducing ESR without increasing the horizontal footprint, as the extended electrode surfaces are stacked vertically within the capacitor body
Data Source
AI summary
Low inductance capacitors include electrodes that are arranged among dielectric layers and oriented such that the electrodes are substantially perpendicular to a mounting surface. Vertical electrodes are exposed along a device periphery to determine where termination lands are formed, defining a narrow and controlled spacing between the lands that is intended to reduce the current loop area, thus reducing the component inductance. Further reduction in current loop area and thus component equivalent series inductance (ESL) may be provided by interdigitated terminations. Terminations may be formed by various electroless plating techniques, and may be directly soldered to circuit board pads. Terminations may also be located on “ends” of the capacitors to enable electrical testing or to control solder fillet size and shape. Two-terminal devices may be formed as well as devices with multiple terminations on a given bottom (mounting) surface of the device. Terminations may also be formed on the top surface (opposite a designated mounting surface) and may be a mirror image, reverse-mirror image, or different shape relative to the bottom surface.