Multilayer Ceramic Capacitor Via Electrode Connection
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Solution Overview
Problem
Multilayer ceramic capacitors face limitations in capacitance due to the configuration of internal and external electrodes, which restricts the placement of dielectric layers and increases Equivalent Series Resistance (ESR), hindering the optimization of current paths.
Innovation Solution
A multilayer electronic component design featuring internal electrodes with through portions and vias that connect external electrodes, allowing for a reduced Equivalent Series Inductance (ESL) and increased capacitance by optimizing the current path within the same chip size, utilizing dielectric and conductive materials to ensure electrical connectivity and disconnection where necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If internal electrodes and external electrodes are connected on side surfaces of the capacitor, then the structure is simple, but it is impossible to further dispose dielectric layers or internal electrodes on the side surface, limiting capacitance
Solution Approach 1:
The patent transitions from side-surface electrode connections to top-surface connections via vias. Internal electrodes extend vertically through dielectric layers and connect to external electrodes through vias formed in the upper dielectric layer, changing the connection dimension from lateral to vertical, thereby enabling additional dielectric layers to be disposed on side surfaces and increasing capacitance.
Solution Approach 2:
The patent applies different connection methods to different regions: vias are formed in specific local regions (upper dielectric layer) to connect internal electrodes to external electrodes, while other regions maintain dielectric layers for capacitance enhancement. This localized approach allows optimized current paths without compromising capacitance.
2Ease of manufacture
If conventional electrode connection is used, then manufacturing is easier, but Equivalent Series Resistance (ESR) increases due to suboptimal current paths
Solution Approach 1:
The patent pre-extends internal electrodes beyond the main body in vertical directions before forming vias. This preliminary extension positions the internal electrodes optimally for via formation, creating shortened current paths that reduce ESR while maintaining manufacturing feasibility through standard via formation processes.
3Productivity
If chip size is reduced for same capacitance, then productivity increases, but ESL may increase due to constrained current path optimization
Solution Approach 1:
The patent utilizes the vertical dimension through vias to connect electrodes, shortening the lateral current path length. This vertical connection approach reduces ESL while maintaining compact chip dimensions, enabling smaller chip sizes for the same capacitance without compromising current path optimization.
Data Source
AI summary
A multilayer electronic component includes first and second external electrodes disposed on one surface of the body, the first internal electrode and the first external electrode being connected by a first via disposed within the body, the second internal electrode and the second external electrode being connected by a second via disposed within the body, the first internal electrode including first and second through portions, and the second internal electrode including third and fourth through portions, the first via penetrating alternately through the first through portion and the third through portion, the second via penetrating alternately through the second through portion and the fourth through portion, and a lead portion of the first via being connected to one end portion of the first external electrode, and a lead portion of the second via being connected to one end portion of the second external electrode.