Multilayer Ceramic Capacitor Via Layout for Higher Capacitance
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Solution Overview
Problem
Conventional multilayer ceramic capacitors with via conductors arranged in a matrix form have a reduced effective area for inner electrodes, leading to decreased electrostatic capacitance.
Innovation Solution
The via conductors are arranged at all virtual lattice points in a specific layout, excluding (m-2)×(n-2) points inside the outermost peripheral points, increasing the effective area for electrostatic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If via conductors are arranged at all virtual lattice points in a matrix form, then the current flow route is shortened and ESL is reduced, but the effective area where inner electrodes are opposed to each other is reduced and electrostatic capacitance is reduced
Solution Approach 1:
The via conductor arrangement is segmented into two groups: first via conductors connected to first inner electrodes and second via conductors connected to second inner electrodes. This segmentation allows the inner electrodes to be arranged in an interlaced pattern, increasing the effective capacitance area while maintaining the matrix form structure for ESL reduction.
Solution Approach 2:
The patent introduces asymmetry by differentiating between first and second via conductors arranged in an interlaced pattern rather than a symmetric matrix. This asymmetric arrangement increases the effective area for electrostatic capacitance while still maintaining short current flow routes for ESL reduction.
2Quantity of substance
If the effective area for inner electrodes is increased to enhance electrostatic capacitance, then the capacitance value increases, but the current flow route lengthens and ESL increases
Solution Approach 1:
The patent transitions from a two-dimensional matrix arrangement to a three-dimensional interlaced arrangement by stacking first and second inner electrodes alternately in the laminate direction. This dimensional change allows increased effective area for capacitance while maintaining short current paths through the via conductors.
Solution Approach 2:
The first and second inner electrodes are nested in an interlaced pattern where they alternate in the laminate direction, with via conductors penetrating through corresponding electrodes. This nesting structure maximizes the effective capacitance area while keeping the current flow routes short.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This arrangement enhances electrostatic capacitance while managing equivalent series resistance (ESR) and equivalent series inductance (ESL), reducing anti-resonance and minimizing ESL increases, even with varying current flows.
Implementation Method 1
an electrostatic capacitance increased as compared with a conventional multilayer ceramic capacitor
Implementation Method 2
first via conductors provided inside the capacitor body and electrically connected to the plurality of first inner electrodes, second via conductors provided inside the capacitor body and electrically connected to the plurality of second inner electrodes
Implementation Method 3
canceling the magnetic fields generated by currents with different polarities each other
Data Source
AI summary
A multilayer ceramic capacitor includes a capacitor body including dielectric layers, first and second inner electrodes, first and second via conductors, and first and second outer electrodes. In a reference layout in which m×n (m and n are each a natural number of 4 or more) virtual lattice points are set in a view of the capacitor body seen in a lamination direction, and in which the first and second via conductors are arranged at all the virtual lattice points, the first and second via conductors are not arranged at least in a portion of (m-2)×(n-2) of the virtual lattice points located inside outermost peripheral virtual lattice points.