MLM-Mapped NAND Latch Access Without Controller RAM Transfer
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Solution Overview
Problem
Conventional flash storage devices are inefficient due to the inability of controllers to directly access data latches in NAND dies, leading to increased operation latency and memory usage, as they rely on transferring data through controller RAM, which results in overhead and reduced performance.
Innovation Solution
The implementation of multi-level memory (MLM) mapped data latches allows direct access by the controller, enabling data to be loaded, processed, and stored within the latches, reducing the need for data transfer to and from controller RAM, and utilizing a CMOS chip with a decoder to decode and store data within the NAND die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If data is transferred from data latches to controller RAM for processing, then data can be accessed by the controller, but operation latency increases and memory usage increases
Solution Approach 1:
The patent extracts the data processing capability from the controller and places it directly in the data latches within the NAND die. The latches can now perform decode and error correction functions independently, eliminating the need to transfer data to controller RAM for processing. This extraction of processing functions resolves the contradiction by enabling controller access to processed data directly from latches without the intermediate RAM transfer step.
Solution Approach 2:
The patent introduces a new intermediary component - the data latch with integrated processing capability - that sits between the memory array and the controller. This enhanced latch acts as a mediator that can process data locally and present processed data to the controller, eliminating the need for controller RAM as an intermediary and reducing operation latency.
2Ease of operation
If data is transferred from data latches to controller RAM, then data can be processed by the controller, but memory usage increases
Solution Approach 1:
The patent extracts the processing functions (decode and error correction) from the controller and embeds them directly in the data latches. This eliminates the need for controller RAM to store processed data, as the latches themselves perform the processing and hold the processed data ready for controller access. This extraction resolves the contradiction by removing the dependency on controller RAM for data processing.
3Productivity
If conventional data transfer through controller RAM is used, then data can be accessed, but overhead increases and performance decreases
Solution Approach 1:
The patent merges the data storage function and data processing function into a single integrated component - the data latch with embedded decode and error correction capabilities. This consolidation eliminates the separate data transfer step to controller RAM and back, simplifying the overall data access process and improving performance by reducing the number of operational steps.
Solution Approach 2:
The patent enables the data latches to serve themselves by performing decode and error correction operations independently without requiring controller intervention or controller RAM involvement. This self-service capability of the latches simplifies the data access architecture and improves performance by eliminating unnecessary data transfer overhead.
Data Source
AI summary
A storage device is provided that allows a controller to directly access bytes of data in data latches connected to memory, as opposed to through controller RAM. The storage device may include a memory, a plurality of data latches connected to the memory, and a controller coupled to each of the data latches. The controller is configured to access one or more bytes of decoded data in one or more of the data latches. For instance, the controller may provide a command including an address for data in the memory, and may process one or more bytes of the data in at least one of the data latches in response to the command. The controller may also store a mapping of addresses for each of the word lines, including the address provided in the command. As a result, operation latency may be reduced and controller RAM savings achieved.