Multi-Level Memory Controller for Unified DDR and NVM Platform
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Solution Overview
Problem
Conventional memory architectures face challenges in providing a flexible and cost-effective solution for desktop systems, as they often require new platforms and SoCs, and have thermal and compatibility issues with on-package memory, limiting OEM flexibility and performance.
Innovation Solution
A common platform is introduced that supports both one-level memory (1LM) and two-level memory (2LM) architectures using a multi-level memory controller (MLMC), allowing for DDR as near memory and NVM as far memory, with the ability to upgrade NM capacity and bandwidth, and using a unified connector for DDR4 and LPDDR4, eliminating the need for on-package memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If on-package memory is used to reduce system BOM and improve integration, then device integration is improved, but thermal issues and compatibility problems arise
Solution Approach 1:
The patent extracts the memory component from the on-package configuration and relocates it to off-package memory slots. This allows the system to maintain the simplified BOM benefits of integrated memory controllers while eliminating the thermal problems associated with on-package memory by physically separating the heat-generating components.
Solution Approach 2:
The patent introduces a multi-level memory controller as an intermediary component that manages both on-package and off-package memory. This mediator enables flexible memory configuration, allowing the system to use off-package memory when thermal issues are concerned while maintaining the ability to use on-package memory when integration is prioritized.
2Productivity
If new platforms and SoCs are developed to support 2LM architecture, then memory performance is improved, but manufacturing cost and complexity increase
Solution Approach 1:
The patent designs a multi-level memory controller with multiple configuration modes that can operate in both 1LM and 2LM architectures. This universal controller can be configured via fuse bits or configuration registers to support different memory arrangements, allowing the same hardware platform to achieve high memory performance without requiring separate manufacturing lines for different architectures.
Solution Approach 2:
The patent implements dynamic configurability in the memory controller through fuse bit settings and configuration registers. This allows the memory architecture to be dynamically adjusted between 1LM and 2LM modes, enabling manufacturers to produce a single platform that can be configured for different performance levels without requiring multiple dedicated hardware designs.
3Adaptability or versatility
If DDR4 and LPDDR4 use separate connectors, then memory compatibility is improved, but device complexity and cost increase
Solution Approach 1:
The patent designs a unified memory connector that can accommodate both DDR4 and LPDDR4 memory modules through a single interface. The multi-level memory controller detects the memory type and configures the appropriate interface, eliminating the need for separate connectors while maintaining full compatibility with both memory standards through software/firmware configuration.
4Temperature
If off-package memory is used instead of on-package memory, then thermal issues are avoided, but system BOM may increase
Solution Approach 1:
The patent extracts memory from the on-package location to off-package memory slots, physically removing the heat-generating component from the processor package. This extraction resolves thermal management issues by improving heat dissipation while the unified memory controller design ensures that the BOM does not significantly increase, as the same controller hardware manages both on-package and off-package memory configurations.
Data Source
AI summary
A processor includes a first memory interface to be coupled to a plurality of memory module sockets located off-package, a second memory interface to be coupled to a non-volatile memory (NVM) socket located off-package, and a multi-level memory controller (MLMC). The MLMC is to: control the memory modules disposed in the plurality of memory module sockets as main memory in a one-level memory (1LM) configuration; detect a switch from a 1LM mode of operation to a two-level memory (2LM) mode of operation in response to a basic input/output system (BIOS) detection of a low-power memory module disposed in one of the memory module sockets and a NVM device disposed in the NVM socket in a 2LM configuration; and control the low-power memory module as cache in the 2LM configuration in response to detection of the switch from the 1LM mode of operation to the 2LM mode of operation.