MLMIMO Models for Metal-Gate Etch Control
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Solution Overview
Problem
Current methods for creating metal-gate structures on wafers face challenges in controlling the thickness and uniformity of Silicon on Insulator (SOI) films, leading to performance degradation due to non-linear etch process behavior and lack of precise control over gate and spacer thickness, especially as feature sizes shrink below 65 nm.
Innovation Solution
The implementation of Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and real-time processing sequences that utilize continuous controllers with metrology data and sensors to optimize etch processes, ensuring precise control over etch steps, gas flows, and temperature, and applying weightings to prioritize process goals, with feedback loops for error correction and noise filtering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etch processes are used for metal-gate structures, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to non-linear etch behavior and inability to control gate and spacer thickness uniformly
Solution Approach 1:
The patent implements a feedback control system using metrology measurements to monitor etch process outcomes and adjust process parameters in real-time. The system measures actual gate and spacer thicknesses after etching steps and uses this data to modify subsequent etch conditions, compensating for non-linear etch behavior and achieving uniform thickness control across varying feature sizes
Solution Approach 2:
The patent dynamically adjusts etch process parameters including gas flow rates, power levels, and pressure based on real-time metrology data and predictive models. This allows the system to adapt to non-linear etch behavior at different feature sizes and maintain precise thickness control without requiring completely different process recipes for each geometry
2Productivity
If feature sizes are reduced below 65 nm, then transistor performance is improved, but manufacturing precision deteriorates due to increased sensitivity to etch process variations
Solution Approach 1:
The patent performs preliminary metrology measurements and predictive modeling before executing etch steps on ultra-small features. The system uses pre-characterized process models to anticipate etch behavior at sub-65nm dimensions and pre-adjusts process parameters to compensate for expected non-linear effects, ensuring thickness uniformity is maintained even as feature sizes shrink
Solution Approach 2:
The patent replaces traditional mechanical/process-trial-based method tuning with computational predictive models and automated feedback control. Machine learning algorithms and physics-based models predict etch outcomes at ultra-small dimensions, allowing precise parameter optimization without relying on iterative mechanical adjustments that introduce variability
3Productivity
If SOI film thickness is reduced to achieve FD SOI, then transistor performance is improved, but manufacturing precision deteriorates due to limitations in thickness control uniformity
Solution Approach 1:
The patent implements feedback control specifically for SOI film thickness management, using metrology measurements to monitor film uniformity and adjust deposition and etch parameters accordingly. This allows the system to maintain the required thickness uniformity even when working with the ultra-thin 25nm FD SOI films needed for high-performance transistors
Data Source
AI summary
The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes.