mLVDS Receiver Buffering Circuit for Lower-Power Parallel Conversion
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Solution Overview
Problem
Conventional multipoint low-voltage differential signaling (mLVDS) receivers in semiconductor devices are inefficient, leading to increased power consumption, larger layout space, and complex signal paths due to the need for multiple serial/parallel conversion units.
Innovation Solution
A buffering circuit that samples and amplifies even-number and odd-number data separately using positive and negative clocks, respectively, and performs serial/parallel conversion to generate parallel data, reducing the number of components required and simplifying the signal path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional mLVDS receiver uses multiple serial/parallel conversion units, then data conversion function is achieved, but power consumption increases
Solution Approach 1:
The patent merges the functions of multiple serial/parallel conversion units into a single buffering circuit that can handle both even and odd data streams simultaneously. The buffering circuit integrates sampling, amplification, and latching functions that previously required separate conversion units, thereby reducing power consumption while maintaining the data conversion capability.
Solution Approach 2:
The buffering circuit is designed to perform multiple functions: it buffers incoming data, separates even and odd data streams, amplifies signals, and performs serial/parallel conversion all within a single unified structure. This multi-functional approach eliminates the need for multiple dedicated conversion units, reducing overall power consumption.
2Area of stationary object
If conventional mLVDS receiver uses multiple serial/parallel conversion units, then data conversion function is achieved, but layout space increases
Solution Approach 1:
The patent combines multiple conversion units into a single integrated buffering circuit, significantly reducing the layout space required. By merging the even data buffering and odd data buffering functions into one circuit block, the physical area occupied is minimized while maintaining full data conversion functionality.
Solution Approach 2:
The buffering circuit employs a nested structure where even data buffering units and odd data buffering units are integrated within a unified framework. The latching circuits are nested within the buffering structure, allowing compact arrangement that minimizes layout space while preserving all necessary functions.
3Device complexity
If conventional mLVDS receiver uses multiple serial/parallel conversion units, then data conversion function is achieved, but signal path becomes complex
Solution Approach 1:
The patent merges multiple signal paths into a single integrated buffering circuit that handles both even and odd data streams through unified sampling and amplification stages. This consolidation simplifies the signal path by eliminating redundant conversion stages while maintaining efficient data conversion throughput.
Solution Approach 2:
The buffering circuit performs preliminary sampling and amplification of incoming data before it enters the serial/parallel conversion stage. By preparing the data in advance within the buffering circuit, the subsequent conversion process is simplified and made more efficient, reducing overall signal path complexity.
Data Source
AI summary
A multipoint low-voltage differential signaling (mLVDS) receiver of a semiconductor device and a buffering circuit of a semiconductor device, includes: an even-number data buffering unit configured to: sample even-number data from input data, amplify and output the even-number data in a section in which a positive clock is activated, and latch the even-number data in a section in which the positive clock is inactivated, and an odd-number data buffering unit configured to: sample odd-number data from the input data, amplify and output the odd-number data in a section in which a negative clock is activated, and latch the odd-number data in a section in which the negative clock is inactivated.