MMA Circuitry for Arbitrary-Size DFT Acceleration

Solution Overview

Problem

Performing computational operations such as discrete Fourier transforms requires significant time, power, or computing resources, particularly for non-power of two or highly composite sizes, where existing techniques are memory-bound and inefficient.

Innovation Solution

Utilizing matrix multiply accumulate (MMA) circuitry, specifically Tensor Cores or Matrix Cores, to perform a first portion of the DFT operation, followed by combining the results with traditional GPU circuits to handle arbitrary transform sizes efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional GPU circuits are used to perform DFT operations, then the system can handle arbitrary transform sizes, but the throughput and performance for non-power of two sized transforms are poor and memory-bound

Engineering Contradiction:

Improvethroughput for non-power of two sized DFTVSAvoidcomputing resources required

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the DFT computation into two distinct parts: a first portion handled by specialized MMA circuitry for power-of-two sized transforms, and a second portion handled by traditional GPU circuits for the remaining computation. This segmentation allows each component to operate in its optimal performance regime, resolving the contradiction between throughput and resource usage.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent creates a unified DFT execution system that combines MMA circuitry and traditional GPU circuits to handle all transform sizes universally. The MMA circuitry handles power-of-two sizes efficiently while the GPU circuits handle arbitrary sizes, making the system multi-functional across different transform size categories.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Productivity

If MMA circuitry is used to perform DFT operations, then throughput and performance for non-power of two sized transforms are enhanced, but the ability to handle arbitrary transform sizes is limited

Engineering Contradiction:

Improveperformance for non-power of two sized DFTVSAvoidsupport for arbitrary transform sizes

Core Design Contradiction:

ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent segments the DFT computation into two distinct parts: a first portion handled by specialized MMA circuitry for power-of-two sized transforms, and a second portion handled by traditional GPU circuits for the remaining computation. This segmentation allows each component to operate in its optimal performance regime, resolving the contradiction between throughput and resource usage.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent creates a unified DFT execution system that combines MMA circuitry and traditional GPU circuits to handle all transform sizes universally. The MMA circuitry handles power-of-two sizes efficiently while the GPU circuits handle arbitrary sizes, making the system multi-functional across different transform size categories.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Loss of time

If legacy methods are used to perform computational operations, then the system is simpler to implement, but significant time and computing resources are consumed

Engineering Contradiction:

Improvecomputational time for DFTVSAvoidcomputing resources used

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent merges MMA circuitry and traditional GPU circuits into a hybrid execution system. The MMA circuitry handles the computationally intensive power-of-two sized transform portions, while the GPU circuits handle the remaining arbitrary size portions, combining the strengths of both architectures to reduce overall computational time and resource consumption.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS12475189B1Techniques to perform operations with matrix multiply accumulate (MMA) circuitry

Publication Date: 2025.11.18 NVIDIA CORP

AI summary

Apparatuses, systems, and techniques to perform operations with matrix multiply accumulate (MMA) circuitry. In at least one embodiment, a processor includes MMA circuitry to perform a first portion of a mathematical operation, one or more first circuits to perform a second portion of the mathematical operation not performed by the MMA circuitry, and one or more second circuits to cause a result of the first portion and the second portion to be combined.