Back-Side Multi-Layer Signal Routing for MMIC Integration
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Solution Overview
Problem
The increasing complexity of millimeter wave systems requires higher circuit integration, which poses challenges in signal routing and interconnection within limited space, especially as frequencies reach into the millimeter wave range, making conventional architectures and existing interconnect methods inadequate.
Innovation Solution
A method for forming a semiconductor structure with a multilayer interconnect structure on a single crystal wafer, utilizing dielectric layers and electrical conductors to route signals and provide thermal conductivity, while allowing for back-side processing and integration of MMICs, enabling efficient use of space on both the front-side and back-side of the integrated circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If higher levels of circuit integration are implemented to achieve advanced performance and reduce system size, then system performance and compactness are improved, but the difficulty of connecting and interconnecting functions increases
Solution Approach 1:
The patent applies multi-layer printed circuit board technology to route signals through multiple vertical layers, transitioning from planar two-dimensional routing to three-dimensional spatial routing. This allows signals to bypass congested areas by traveling through different layers and using vias for vertical transitions, thereby resolving the contradiction between high circuit integration and signal routing complexity.
Solution Approach 2:
The patent segments the circuit board into multiple functional layers, each dedicated to specific signal types or functions. By dividing the routing problem into layer-specific segments, the complexity of interconnecting buried functions is reduced, as each layer can be optimized independently for its specific routing requirements while collectively solving the overall interconnection challenge.
2Area of moving object
If antenna element spacing is reduced to achieve smaller phased array antenna systems, then system size is reduced, but the available area for transmit and receive circuitry decreases
Solution Approach 1:
The patent utilizes multi-layer PCB construction to move circuitry from the limited planar area on the front side of the MMIC into the vertical dimension through additional layers. This three-dimensional routing approach effectively increases the available circuitry area without increasing the physical footprint of the antenna elements, thereby resolving the contradiction between compact antenna size and sufficient circuitry area.
3Reliability
If conventional T/R module architectures in sealed packages are used, then system reliability is maintained, but system size and integration flexibility are limited
Solution Approach 1:
The patent merges multiple discrete T/R module functions into a single integrated MMIC chip, combining transmit and receive circuits, phase shifters, and other functions on one monolithic device. This integration maintains reliability through proven MMIC technology while dramatically increasing integration density and reducing system size, thereby resolving the contradiction between reliability and integration density.
4Adaptability or versatility
If interconnection and routing of signals are implemented to provide minimal functionality, then system functionality is achieved, but precious space is occupied
Solution Approach 1:
The patent employs multi-layer routing to move signal interconnections from the limited two-dimensional plane into the third dimension through vertical vias and stacked layers. This allows minimal functionality to be achieved with compact routing that occupies significantly less planar area, as signals can travel vertically between layers rather than requiring extensive lateral routing space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach optimizes space usage, allowing for the integration of essential system functions and efficient interconnection of d.c. bias, digital control, and r.f. connections, making it feasible to fit compacted circuits within the limited area, enhancing the performance of millimeter wave systems.
Implementation Method 1
the electrical conductors and dielectric layers providing a thermal conductor between a region exterior of the wafer and a region in thermal contact with the active device
Data Source
AI summary
A method includes providing a single crystal wafer having MMIC chips. Each chip has an active device in a first surface portion of a semiconductor substrate provided by the wafer and an electrical interconnect having a first portion disposed on a second surface of the semiconductor substrate. The semiconductor substrate structure has a via therethrough, a second portion of the electrical interconnect passing though the via and being electrically connected to the active device. A multilayer interconnect structure is formed on the wafer providing a signal routing section on the second surface portion of a corresponding one of the chips. Each section has dielectric layers and an electrical conductor, such electrical conductor being electrically coupled to the active device to route an electrical signal to such active device. Each chip and the corresponding signal routing section are separated from the wafer.