MMIC Bias Pad Layout for Shorter Bond Wires and Lower Inductance
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Solution Overview
Problem
The increase in wire length and inductance value due to the proximity of multiple DC pads and MIM capacitors in semiconductor devices leads to ineffective short-circuiting of low-frequency signals, causing oscillation risks.
Innovation Solution
The arrangement of pads between DC pads and MIM capacitors parallel to the capacitors, allowing for shorter wire lengths and reduced inductance values, independent of MIM capacitor size, by increasing the freedom of wire bonding positions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple MIM capacitors are laterally arranged side by side to be connected to DC pads, then the capacitors can be mounted on the bias substrate, but the wires become oblique and their length increases, causing inductance value to increase
Solution Approach 1:
The pads are arranged in a linear array extending in the lateral direction (parallel to the row of MIM capacitors) rather than being positioned directly above or below. This dimensional arrangement allows wires to connect to intermediate points along the pad array, reducing wire length and inductance while still providing multiple connection points for multiple capacitors
Solution Approach 2:
The linear array of pads acts as an intermediary structure between the DC pads and MIM capacitors. By providing multiple pad positions along the array, the system enables shorter wire connections while maintaining the necessary electrical connections, effectively mediating between the spatial constraints of component placement and the electrical requirements of low-inductance connections
2Reliability
If the number of wires is increased to reduce total inductance value through parallelization, then inductance can be reduced, but the upper limit of wire number is constrained by the size of MIM capacitors
Solution Approach 1:
The single large pad is segmented into multiple smaller pads arranged in a linear array. This segmentation provides multiple discrete bonding positions for wires while keeping each individual pad small enough to fit within the space constraints imposed by the MIM capacitor size, thereby enabling increased wire count for inductance reduction without exceeding physical layout limits
3Area of stationary object
If MIM capacitors are arranged close to DC pads, then the layout is compact, but wire length increases and inductance value increases, preventing effective short-circuiting of low-frequency signals
Solution Approach 1:
Instead of arranging pads directly adjacent to capacitors in a compact but high-inductance configuration, the pads are arranged in a linear array that extends laterally. This allows the selection of intermediate bonding positions that optimize the balance between layout compactness and wire length, maintaining effective low-frequency signal short-circuiting while preserving space efficiency
Data Source
AI summary
A semiconductor device includes: an MMIC having a DC pad; a bias substrate; a plurality of MIM capacitors mounted on the bias substrate; a plurality of pads provided on the bias substrate and respectively connected to overlying electrodes of the MIM capacitors; and a wire connecting the DC pad to any one of the plurality of pads, wherein the plurality of pads are arranged between the DC pad and the plurality of MIM capacitors in a planar view, and extend parallel to a row of the plurality of MIM capacitors laterally arranged side by side.