MMIC Coplanar Waveguide Simulation for Thin Substrate Resonance
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Solution Overview
Problem
Existing MMIC designs using coplanar waveguides on thin substrates like diamond face challenges due to limited space for connections between local and signal ground planes, leading to unwanted resonances and electromagnetic coupling effects that degrade performance, as current simulation methods fail to accurately model the impact of backside metallization.
Innovation Solution
A method for simulating coplanar waveguide sections in MMICs by mathematically modeling local ground planes with connectable ports, allowing for accurate representation of currents and accounting for the backside ground plane effects through subdividing the circuit, forming extended ports, and performing electromagnetic simulations to capture the substrate's impact on circuit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If thin substrates (100 um diamond) are used to reduce size and improve thermal performance, then thermal conductivity and size are improved, but unwanted resonances and electromagnetic coupling effects increase due to limited space for ground plane connections
Solution Approach 1:
The patent introduces an intermediate modeling layer that represents the backside ground plane's electromagnetic influence on the front-side CPW structure. This intermediary model captures the harmful coupling effects without requiring physical modification of the thin substrate, allowing designers to account for resonances and electromagnetic coupling in simulations while maintaining the thermal and size benefits of thin substrates.
Solution Approach 2:
The patent creates a simplified copy or representation of the backside ground plane's electromagnetic effects through an equivalent circuit model. This copy allows the harmful effects to be studied and mitigated in simulation without altering the physical thin substrate structure, preserving both thermal performance and size advantages while enabling correction of electromagnetic issues.
2Device complexity
If conventional simulation methods are used, then simulation simplicity is maintained, but accuracy of modeling backside metallization effects is insufficient
Solution Approach 1:
The patent segments the MMIC structure into distinct modeling zones: the front-side CPW region, the thin substrate region, and the backside ground plane region. Each zone is represented with appropriate modeling techniques, with the substrate region using an equivalent circuit model that captures electromagnetic coupling without requiring full-wave simulation of the entire structure, thus balancing accuracy and complexity.
Solution Approach 2:
The patent transforms the three-dimensional electromagnetic problem into a two-dimensional equivalent circuit problem by changing the modeling parameters. Instead of simulating the full 3D electromagnetic fields through the thin substrate, the invention uses equivalent circuit parameters (inductances, capacitances, resistances) that represent the substrate's electromagnetic effects, significantly reducing simulation complexity while maintaining accuracy.
3Object-affected harmful factors
If CPW transmission line dimensions are restricted to less than 1/3 of substrate height, then impact of backside ground metallization is moderated, but line widths become too narrow and add significant loss
Solution Approach 1:
The patent applies preliminary action by incorporating the backside ground plane's electromagnetic effects into the simulation model before finalizing CPW transmission line dimensions. This allows designers to optimize line widths and gaps for minimal loss while accounting for substrate coupling effects in advance, rather than being forced to use overly conservative dimension restrictions that increase loss.
Solution Approach 2:
The patent implements feedback by using simulation results that include backside ground plane effects to iteratively optimize CPW transmission line dimensions. The equivalent circuit model provides feedback on how different line geometries interact with the substrate, allowing designers to find optimal dimensions that minimize both electromagnetic coupling and conductor losses.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the accuracy of MMIC design simulations by properly modeling the backside metallization effects, reducing unwanted resonances and improving the electrical performance of MMICs on thin substrates by ensuring accurate current representation and propagation modes.
Implementation Method 1
a plurality of coplanar waveguide transmission line sections disposed on the top surface of the substrate for electrically interconnecting the active and passive electrical elements
Implementation Method 2
the backside of the MMIC substrates provided with a metal, such as thick electro-plated gold, to enable a thermal conductive bond between the metal and an underlying heat sink structure
Implementation Method 3
The local ground planes (i.e., the CPW ground planes) are electrically connected to the backside signal ground
Implementation Method 4
the local ground on the substrate front-side and the signal ground plane on the backside of the chip form an electrical network that supports parallel plate mode propagation. The parallel plate mode generates unwanted resonances and other deleterious electromagnetic coupling effects
Data Source
AI summary
A MMIC having: a substrate; a plurality of active and passive electrical elements disposed on a top surface of the substrate; a plurality of coplanar waveguide transmission line sections disposed on the top surface of the substrate for electrically interconnecting the active and passive electrical elements; an electrical conductor disposed on a bottom surface of the substrate under the coplanar waveguide section. Edges of ground plane conductors of the coplanar waveguide (CPW) sections have slots therein in regions thereof connected to the active and passive devices. The design of such circuit includes mathematical models of the CPW with the pair of local ground planes and the strip conductor thereof have relatively narrow connectable ports.