Millimeter-Wave IC Package Vertical Stacking

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Solution Overview

Problem

Current millimeter wave integrated circuit packages face challenges in integrating numerous antenna elements and ICs due to routing congestion, large package size, increased cost, and heat removal difficulties, particularly when many antenna elements need to be individually driven by distinct RF ports.

Innovation Solution

A double-sided surface mount packaging scheme is implemented, where antennas are located on the top layers of a substrate and ICs are on the bottom, using a multi-layer substrate with embedded antenna arrays and MMICs flip-chip mounted to the substrate, along with a compensated vertical interconnect scheme to manage millimeter-wave signals effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If both antenna and IC are located on the same surface, then acceptable performance is achieved, but routing congestion limits the number of elements

Engineering Contradiction:
ImproveperformanceVSAvoidrouting congestion
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent transitions from a two-dimensional planar layout to a three-dimensional stacked architecture. Antennas are positioned on the top surface while ICs are mounted on the bottom surface of the substrate, utilizing the vertical dimension to eliminate routing congestion and enable independent optimization of each component layer.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If ICs and antennas are located on the same surface with clearance, then performance is maintained, but package size increases

Engineering Contradiction:
ImproveperformanceVSAvoidpackage size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

By stacking components vertically on opposite surfaces of the substrate, the patent reduces the horizontal footprint required. The top layer accommodates antennas while the bottom layer houses ICs, allowing compact packaging without compromising performance through maintained clearance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Quantity of substance

If package size increases, then more elements can be accommodated, but cost increases and substrate may become too large to manufacture

Engineering Contradiction:
Improvenumber of elementsVSAvoidsubstrate manufacturability
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The vertical stacking approach enables a high density of antenna elements and ICs within a compact substrate footprint. This three-dimensional arrangement increases the quantity of elements that can be integrated without exceeding substrate size limits for manufacturing.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

4Device complexity

If ICs are located on the top layer with antennas, then integration is achieved, but heat removal from ICs becomes difficult

Engineering Contradiction:
Improveintegration levelVSAvoidheat removal
Core Design Contradiction:
Device complexityVSTemperature

Solution Approach 1:

Placing ICs on the bottom surface of the substrate provides direct access to the rear side for thermal management. Heat sinks and cooling structures can be attached to the back of the ICs, enabling efficient heat dissipation while maintaining high-level integration with antennas on the top surface.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentEP2178119B1Surface mountable integrated circuit package
Publication Date: 2018.06.20 QUALCOMM INC
  • EP2178119B1 patent drawingFigure 1
  • EP2178119B1 patent drawingFigure 2
  • EP2178119B1 patent drawingFigure 3

AI summary

An integrated circuit (IC) package is disclosed. The IC package includes a substrate having top, middle and bottom layers, an array of millimeter-wave antennas embedded on the top layer of the substrate and a monolithic microwave integrated circuit (MMIC) mounted on the bottom layer of the substrate. In one embodiment, the second level interconnect for surface-mounting on a printed circuit board (PCB) is provided on the bottom layer of the substrate.