Multi-Stage MMIC Signal Distribution for Low Phase and Gain Mismatch

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Solution Overview

Problem

Existing electrical signal processing devices for radio direction finders with multiple receivers face challenges in minimizing phase and gain differences while maintaining a compact footprint, as current devices with sufficient performance are bulkier and less efficient.

Innovation Solution

The proposed solution involves a processing device with multiple stages of monolithic microwave integrated circuits connected in a specific configuration, where each stage generates minimal phase and gain differences, and the circuits are arranged to reduce the device's footprint by distributing terminals uniformly around a central hub.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If state-of-the-art processing devices with 5 or more inputs/outputs are used to achieve sufficient phase difference and gain difference performance, then the phase and gain differences are minimized, but the device footprint becomes very bulky

Engineering Contradiction:
Improvephase difference and gain difference performanceVSAvoiddevice footprint
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The processing device is divided into multiple stages (at least two stages), where each stage processes signals for a subset of terminals. This segmentation allows the device to handle multiple terminals with controlled phase and gain differences while reducing the overall footprint compared to a single-stage monolithic design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture where multiple stages are arranged vertically. This dimensional change enables better signal distribution and reduces the horizontal footprint while maintaining performance through controlled inter-stage connections.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If a large number of receivers (N ≥ 5) are connected to the processing device, then the device can support more receivers for radio direction finding, but maintaining low phase and gain differences becomes more difficult

Engineering Contradiction:
Improvenumber of receivers supportedVSAvoidphase difference and gain difference consistency
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The device segments the N terminals into groups, with each stage handling a subset of terminals. This segmentation enables the device to support a large number of receivers while maintaining consistent phase and gain differences by limiting the complexity within each stage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The multi-stage architecture provides dynamic signal processing capabilities, where each stage can be independently optimized and adjusted. This dynamic structure allows the device to maintain performance consistency across a variable number of terminals by activating only the necessary stages.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP4395170A1Device for processing electrical signals
Publication Date: 2024.07.03 THALES SA
  • EP4395170A1 patent drawingFigure 1
  • EP4395170A1 patent drawingFigure 2
  • EP4395170A1 patent drawingFigure 3

AI summary

The electrical signal processing device (10) comprises: - an electrical signal processing module (60); - a first terminal (50) and N second terminals (52), each connected to the module (60) and capable of receiving an electrical signal, processing or distributing a processed electrical signal, N being an integer greater than or equal to 5. The module (60) comprises M stages (62) successively connected between the first terminal (50) and the second terminals (52), M being an integer greater than or equal to 2, a first stage (62) comprising a first integrated circuit (64); for K an integer between 2 and M, the Kth stage (62) comprises at least one set (66) of Kth integrated circuits (64), the Kth circuits (64) of each set (66) being connected to a respective K-1st circuit (64) of the K-1st stage (62).