MMIO Storage Mapping for Low-Latency Device Data Transfer
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Solution Overview
Problem
The increasing interaction delay between the CPU and DMA controller in high-speed I/O operations limits the data transmission rate in modern computer systems, reducing the efficiency of CPU utilization and overall system performance.
Innovation Solution
Mapping storage space of a second device to the memory-mapped input/output (MMIO) address space of a first device allows the processor to directly send instructions to a storage controller, eliminating the need for intermediate memory operations and reducing interaction delays, thereby enhancing data transmission rates between devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If asynchronous DMA solution is used with CPU interaction for DMA request and interrupt, then device compatibility and control flexibility are improved, but interaction delay between CPU and DMA controller increases, limiting data transmission rate
Solution Approach 1:
The patent extracts the DMA control functionality from the CPU by implementing a standalone storage controller with dedicated control logic. The storage controller independently handles DMA requests, data transmission, and interrupt generation without requiring CPU intervention during the transmission process, thereby eliminating CPU-DMA interaction delays while maintaining device compatibility through standardized interfaces.
Solution Approach 2:
The storage controller implements self-service capability by autonomously managing the entire DMA process including receiving DMA requests, controlling data flow between devices, and generating interrupts only when transmission completes or errors occur. This self-managed approach eliminates continuous CPU-DMA interaction while preserving system adaptability through programmable control registers.
2Reliability
If CPU is largely occupied with data migration tasks, then data transmission control is improved, but CPU capability to participate in actual computing is reduced
Solution Approach 1:
The patent segments the data transmission control function from the CPU by implementing a dedicated storage controller that independently handles all DMA operations. The CPU retains high-level control through initialization and interrupt handling, while the storage controller manages the actual data migration process, enabling parallel execution of CPU computing tasks and DMA transmissions without compromising transmission reliability.
Solution Approach 2:
The storage controller acts as an intermediary between the CPU and peripheral devices for data transmission operations. It receives control parameters from the CPU, autonomously executes data migration, and reports completion or errors to the CPU, thereby freeing the CPU from direct involvement in data movement while maintaining reliable control through the intermediary storage controller.
3Speed
If storage space of second device is mapped to MMIO address space of first device, then direct access and data transmission rate are improved, but address space complexity and mapping management are increased
Solution Approach 1:
The patent implements preliminary action by pre-configuring the MMIO address space mapping between the first device and storage space of the second device before data transmission operations. The storage controller maintains mapping tables that associate MMIO addresses with physical storage addresses, enabling direct address translation and access without runtime complexity, thus achieving high-speed transmission while managing address space complexity through advance setup.
Data Source
AI summary
Embodiments of this application disclose a data processing apparatus and method, and a related device. Storage space of a second device is mapped to a memory-mapped input/output MMIO address space of the first device. N MMIO addresses in the MMIO address space of the first device are in a one-to-one correspondence with N first storage addresses in the storage space of the second device. The processor is configured to send a first instruction to the storage controller, where the first instruction includes a target MMIO address. The storage controller is configured to: receive the first instruction, and determine a first storage address corresponding to the target MMIO address; and send a first operation instruction to the second device, where the first operation instruction corresponds to the first instruction, and the first operation instruction includes the first storage address.