Memory-Mapped Register Access Control via Segmented Firewalls
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Solution Overview
Problem
In systems-on-a-chip (SOCs), critical and non-critical processes share resources, posing a risk that non-critical processes can overwrite or corrupt memory-mapped registers (MMRs) used by critical processes, which is not effectively addressed by existing technologies.
Innovation Solution
The implementation of multiple proxy addresses and firewalls for MMRs, where critical processes access MMRs through one region (Proxy1) and non-critical processes through another (Proxy0), with a claim logic circuit managing access based on claim fields and permission levels to ensure exclusive write access for critical processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If non-critical processes are allowed to access shared resources in an SOC, then resource utilization and productivity are improved, but the risk of overwriting or corrupting MMRs used by critical processes increases
Solution Approach 1:
The patent segments the address space into multiple regions (first address region and second address region) and implements separate firewall mechanisms for each region. The first firewall handles write requests from the first address region with different protection rules, while the second firewall handles write requests from the second address region, allowing differentiated access control to protect critical MMRs while permitting non-critical access where appropriate.
2Reliability
If complex hardware firewalls are implemented for each MMR to prevent corruption, then reliability is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent implements a universal firewall structure where a single first firewall and a single second firewall handle protection for multiple MMRs across different address regions. These firewalls use permission levels and address region identification to provide differentiated protection for multiple registers without requiring individual firewall hardware for each MMR, thereby reducing overall device complexity while maintaining comprehensive protection.
Data Source
AI summary
A system includes a memory-mapped register (MMR) associated with a claim logic circuit, a claim field for the MMR, a first firewall for a first address region, and a second firewall for a second address region. The MMR is associated with an address in the first address region and an address in the second address region. The first firewall is configured to pass a first write request for an address in the first address region to the claim logic circuit associated with the MMR. The claim logic circuit associated with the MMR is configured to grant or deny the first write request based on the claim field for the MMR. Further, the second firewall is configured to receive a second write request for an address in the second address region and grant or deny the second write request based on a permission level associated with the second write request.