MMRSCSSE Layout Placement for IC Node Spacing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Automated design tools for generating integrated circuits (ICs) often create layouts with inadequate spacing between critical nodes, compromising the effectiveness of radiation-hardened designs due to their focus on spatial efficiency, leading to tedious and time-consuming manual adjustments for Sequential State Elements (SSEs) with redundancy.
Innovation Solution
An electronic computation system loads a gate-level netlist into an EDA program to generate an IC layout with Multi-Mode Redundant (MMR) pipeline circuits, initially placing and then rendering Multi-Mode Redundant Self-Correcting Sequential State Elements (MMRSCSSE) immotile, allowing for optimized placement of remaining logic without compromising critical node spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If EDA programs place components as close together as possible to create spatially efficient designs, then area efficiency is improved, but critical node spacing is compromised
Solution Approach 1:
The patent applies preliminary action by first placing the MMRSCSSE layouts in the IC layout and rendering them immotile before placing the remaining logic components. This preliminary placement of critical SSE elements with adequate spacing allows the subsequent automated placement to optimize the remaining areas without compromising the spacing requirements of the radiation-hardened state elements.
2Reliability
If manual placement adjustments are made to ensure critical node spacing for SSEs with redundancy, then reliability is improved, but time consumption increases
Solution Approach 1:
The patent automates the preliminary placement of MMRSCSSE layouts with proper spacing before the main routing process. By pre-placing these critical elements and rendering them immotile, the system eliminates the need for time-consuming manual adjustments while ensuring adequate critical node spacing for radiation hardening.
Solution Approach 2:
The EDA program performs self-service by automatically handling the placement of MMRSCSSE layouts with appropriate spacing requirements. The system incorporates the spacing constraints directly into the automated placement process, allowing the tool to serve itself rather than requiring manual human intervention for these critical elements.
3Reliability
If redundancy is added to SSEs to correct soft errors, then reliability is improved, but layout complexity increases
Solution Approach 1:
The patent segments the IC layout into distinct regions: one for MMRSCSSE layouts with their required spacing, and another for the remaining logic components. This segmentation allows the redundant SSE elements to be placed with adequate spacing for radiation hardening while the automated placement optimizes the remaining areas, managing the overall layout complexity systematically.
Data Source
AI summary
This disclosure relates generally to computerized systems and methods of producing a physical representation of an in silico Integrated Circuit (IC) having an in silico Multi-Mode Redundant (MMR) pipeline circuit. An IC layout of the in silico IC is initially generated with the electronic design automation (EDA) program. Multi-Mode Redundant Self-Correcting Sequential State Element (MMRSCSSE) layouts are then rendered immotile while initial redundant Combinational Logic Circuit (CLC) layouts are removed from the IC layout after the MMRSCSSE layouts have been rendered immotile. By first placing the MMRSCSSE layouts and then rendering them immotile, the remaining logic can be placed again and optimized without compromising critical node spacing. As such, the described method provides for a more efficient way to create the IC layout of the in silico IC while maintaining critical node spacing.