MMU External Caching for Translation Latency Reduction
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Solution Overview
Problem
Current memory management units (MMUs) experience high translation latency due to the need for frequent access to page table entries (PTE) data, which can be located externally, leading to increased latency and reduced computing system efficiency.
Innovation Solution
The MMU requests and obtains PTE data with coherent ownership, and if the source location is external, performs a lateral cast out to a local high-level cache, directing subsequent requests to this cache to reduce latency and improve efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the MMU frequently accesses PTE data from external memory locations, then the system can maintain accurate page table information, but translation latency increases and system efficiency decreases
Solution Approach 1:
The patent implements a page table cache that pre-loads and stores PTE data locally before it is needed for translation operations. By anticipating future translation needs and preparing the data in advance, the system reduces translation latency while maintaining data accuracy through coherent ownership protocols that ensure the cached data remains valid.
Solution Approach 2:
The patent introduces a page table cache as an intermediary structure between the MMU and external memory. This cache mediates access to PTE data, allowing the MMU to retrieve translations from local cached data rather than directly from external memory, thereby reducing latency while maintaining coherence through ownership tracking mechanisms.
2Loss of energy
If the MMU accesses PTE data from external memory locations, then the system can maintain memory consistency, but communication fabric traffic increases
Solution Approach 1:
The patent extracts frequently accessed PTE data from external memory and stores it locally in a page table cache within the MMU. By taking out this critical data from the external memory system, the patent reduces communication fabric traffic and energy consumption while maintaining memory consistency through coherent ownership protocols that track and manage the cached data's validity state.
3Productivity
If the system uses a local high-level cache for PTE data, then translation latency is reduced, but device complexity increases
Solution Approach 1:
The patent implements self-service mechanisms within the page table cache, where the cache automatically manages its own coherence state and ownership tracking. The coherent ownership protocol enables the cache to autonomously determine when data is valid and when it needs to be updated, reducing translation latency while minimizing the complexity burden on the MMU by embedding management logic within the cache structure itself.
Data Source
AI summary
Reducing translation latency within a memory management unit (MMU) using external caching structures including requesting, by the MMU on a node, page table entry (PTE) data and coherent ownership of the PTE data from a page table in memory; receiving, by the MMU, the PTE data, a source flag, and an indication that the MMU has coherent ownership of the PTE data, wherein the source flag identifies a source location of the PTE data; performing a lateral cast out to a local high-level cache on the node in response to determining that the source flag indicates that the source location of the PTE data is external to the node; and directing at least one subsequent request for the PTE data to the local high-level cache.