Memory Management Unit FIFO Retry Queue for Cache Miss Handling
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Solution Overview
Problem
In microprocessor systems, memory management units (MMUs) face inefficiencies due to cache misses during memory access requests, leading to blocking of subsequent memory accesses until the missed access is resolved, which can be costly in terms of latency and system throughput.
Innovation Solution
Implementing a first-in, first-out (FIFO) retry queue mechanism within the MMU to handle memory access requests that result in cache misses, allowing these requests to be retried later without blocking other memory accesses, thereby maintaining system operation and reducing the need for complex buffering and resolution mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If memory access requests causing cache misses are blocked until resolution, then address translation accuracy is maintained, but system throughput deteriorates
Solution Approach 1:
The patent segments memory access requests into two categories: those that can be immediately serviced and those requiring cache miss handling. By separating the handling path for cache hit and cache miss scenarios, the system maintains accurate address translation while allowing non-blocking operation for cache hits, thus resolving the contradiction between translation accuracy and system throughput.
Solution Approach 2:
The patent introduces a buffer as an intermediary component between the memory management unit and the cache memory. This buffer temporarily holds memory access requests that cause cache misses, allowing the MMU to continue processing other requests while the buffered requests are resolved asynchronously. This mediator mechanism maintains translation accuracy while preventing throughput degradation.
2Device complexity
If cache miss handling is implemented without buffering, then device complexity is reduced, but loss of time increases
Solution Approach 1:
The patent implements preliminary action by buffering memory access requests before they are fully resolved. By anticipating that cache misses will occur and preparing a buffer in advance, the system can quickly store and later retrieve these requests without ad-hoc complex handling logic. This preliminary preparation reduces both the complexity of the handling mechanism and the time loss associated with cache misses.
3Duration of action of stationary object
If complex buffering arrangements are used to handle cache misses, then memory access continuity is improved, but device complexity increases
Solution Approach 1:
The patent extracts the cache miss handling logic from the main memory access path by using a simple buffer that only intervenes when cache misses occur. This extraction allows the main memory access continuity to be maintained through the simple buffer mechanism without requiring complex buffering arrangements, thus resolving the contradiction between access continuity and device complexity.
Data Source
AI summary
A memory management arrangement includes a memory management unit, a cache memory and a queue arrangement. The queue is a first-in, first-out (FIFO) buffer which can queue failed memory access requests and return them as inputs to the memory management unit via the bus 5 for retrying through the memory management unit at a later time. If a memory access request sent to the memory management unit experiences a cache “miss”, instead of blocking memory access requests until the required address data has been loaded into the cache, the memory management unit operates to place the failed memory access request in the replay queue, and allows subsequent memory access requests to continue. The failed memory access requests in the queue are then continuously circulated through the memory management unit from the queue alternately with new memory access requests from other access initiators.