Memory Management Unit Master Device Indexing
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Solution Overview
Problem
In systems with multiple master devices, the shared memory management unit (MMU) and translation lookaside buffer (TLB) can lead to performance limitations due to thrashing, where activities of one master device affect others, and existing solutions like adding an extra bit to TLB entries increase size without fully addressing the issue.
Innovation Solution
A memory management unit that selects entries based on both the virtual address and the identifier of the requesting master device, using an index generation unit to generate an index for the internal storage unit, allowing for unique allocation of entries to each master device, potentially using hash functions and arbiter units to prioritize and optimize memory access requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a shared MMU/TLB is used to occupy limited area on SoC device, then area is reduced, but performance deteriorates due to thrashing between multiple master devices
Solution Approach 1:
The patent segments the single shared TLB into multiple master device-specific TLB structures by incorporating master device identifiers into the indexing mechanism. Each master device has its own set of TLB entries that can be independently accessed, preventing thrashing while maintaining a compact implementation suitable for SoC area constraints.
2Adaptability or versatility
If an extra bit is added to each TLB entry to indicate master association, then master tracking is enabled, but TLB entry size increases
Solution Approach 1:
The patent merges the master device identifier with the virtual address to form a composite index key. Instead of adding separate storage for master identification, the master ID is integrated into the indexing structure itself, allowing the same TLB entry to be selectively accessed by different master devices without increasing entry size.
3Area of stationary object
If a single TLB is shared among multiple master devices, then area is reduced, but thrashing occurs when multiple masters use the same TLB entry
Solution Approach 1:
The patent introduces master device identifiers as an intermediary element in the TLB indexing process. This intermediary allows the system to distinguish between different master devices accessing the same virtual address, preventing unwanted overwriting of TLB entries and eliminating thrashing while maintaining a compact TLB structure.
Data Source
AI summary
A data processing apparatus is provided comprising a plurality of master devices configured to issue memory access requests including virtual addresses. A memory management unit is configured to receive memory access requests and to translate a virtual address included in a memory access request from a requesting master device into a physical address indicating a storage location in memory. The memory management unit has an internal storage unit having a plurality of entries wherein indications of corresponding virtual address portions and physical address portions are stored. The memory management unit is configured to select an entry of the internal storage unit in dependence on the virtual address and an identifier of the requesting master device. Conflict between the master devices in their usage of the internal storage unit is thus avoided.