Error-Detecting Circuit Between MMU and Memory

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Solution Overview

Problem

Existing data processing systems, particularly in safety-critical applications like automotive and medical environments, face challenges in detecting and handling transient faults that can lead to erroneous memory transactions, which may corrupt persistent data structures and impact subsequent processing operations.

Innovation Solution

Incorporating an error-detecting circuit between the Memory Management Unit (MMU) and memory, where memory addresses are configured to include an error-detecting code, allowing the circuit to validate memory addresses before transactions proceed, thus detecting and flagging errors caused by transient faults.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an error-detecting circuit is added between the MMU and memory, then the reliability of memory transactions is improved, but the device complexity increases

Engineering Contradiction:

Improvememory transaction integrityVSAvoidsystem architecture

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

An error-detecting circuit is introduced as an intermediary component between the MMU and memory. This circuit validates memory addresses by checking error-detecting codes before transactions reach memory, thereby improving reliability without requiring fundamental changes to the core memory subsystem architecture.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

Error detection is performed preliminarily at the memory address validation stage, before actual memory transactions occur. By checking error-detecting codes on addresses before they are used for data access, the system prevents erroneous transactions from reaching memory, improving reliability while keeping the intervention minimal and localized.

Inventive Principle:

Principle #10Preliminary action

2Measurement precision

If error-detecting codes are incorporated into memory addresses, then the precision of error detection is improved, but the loss of information increases due to reduced addressable memory space

Engineering Contradiction:

Improveerror detection accuracyVSAvoidaddressable memory space

Core Design Contradiction:

Measurement precisionVSLoss of information

Solution Approach 1:

The memory address structure is modified by incorporating error-detecting code bits as additional parameters within the address format. This allows the system to validate addresses with higher precision by checking these code bits, while the reduction in addressable space is accepted as a trade-off for improved error detection capability.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

Error-detecting codes are generated as copies or derived values from the original memory address data. Rather than replacing address bits entirely, the system creates redundant code bits that mirror essential address information, enabling validation without completely sacrificing address space efficiency.

Inventive Principle:

Principle #26Copying

Data Source

PatentUS11775380B2Data processing systems

Publication Date: 2023.10.03 ARM LTD

AI summary

A data processing system comprises a memory, a processing unit, a MMU operable to process memory transactions for the processing unit; and an error-detecting circuit located between the MMU and the memory. The MMU is configured to determine from respective memory address mappings corresponding memory addresses to which memory transaction applies. The determined memory addresses comprise a first part representing a memory location and a second part representing an error-detecting code generated using the first part of the memory address. The error-detecting circuit can then check using the error-detecting code for the memory address whether the memory address received by the error-detecting circuit is valid.