MMU Hardware Assistance for Guest Page Table Coherence

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Solution Overview

Problem

Existing virtualization systems face challenges in maintaining coherence between shadow page tables and guest page mappings, leading to increased page fault overheads and performance degradation, especially when relying on page protection mechanisms.

Innovation Solution

A memory management unit (MMU) is configured to identify and record update information for guest page mappings that target memory pages containing guest page tables, allowing for efficient reestablishment of coherence between shadow page tables and guest page mappings, thereby reducing overheads associated with exception handling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If page protection mechanisms are used to intercept guest writes to memory pages containing guest page tables, then coherence between shadow page tables and guest page tables is maintained, but page fault overheads increase

Engineering Contradiction:

Improvecoherence between shadow page tables and guest page tablesVSAvoidpage fault overheads

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The system pre-identifies memory pages that contain guest page table information by setting a traced write indication bit in the shadow page table entry before guest writes occur. This preliminary marking allows the MMU to recognize and handle these pages specially, avoiding the need for general page protection interception and reducing page fault overheads while maintaining coherence.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The MMU automatically records update information for shadow page table entries when it detects a traced write indication, without requiring external intervention or handler processing. This self-service mechanism allows the hardware to maintain coherence autonomously, reducing the overhead associated with software handlers and page fault interception.

Inventive Principle:

Principle #25Self-service

2Productivity

If shadow page tables complete the mapping from GVPNs to PPNs, then direct execution of guest code on underlying hardware is enabled, but complexity of memory mapping information increases

Engineering Contradiction:

Improvedirect execution of guest codeVSAvoidmemory mapping information

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The memory mapping system is segmented into two distinct components: guest page tables (maintained by the guest OS) and shadow page tables (maintained by the virtualization system). This segmentation allows each layer to operate independently with its own management rules, enabling direct execution while keeping the complexity localized to the shadow page table layer without affecting guest OS operations.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Shadow page tables act as an intermediary layer between the guest virtual address space and the physical memory system. This intermediary structure enables the virtualization system to provide direct execution capabilities by translating GVPNs to PPNs without requiring guest OS involvement, while the intermediary itself manages the complexity of maintaining multiple mapping layers.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Productivity

If traced write indication is set for shadow page mappings, then update information can be recorded efficiently, but overhead for tracking individual writes increases

Engineering Contradiction:

Improveaccumulation of memory access informationVSAvoidtracking overhead

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The system replaces software-based page fault interception and handling mechanisms with hardware-based automatic tracking in the MMU. By substituting the mechanical/software approach with a hardware-level mechanism that automatically records writes when traced write indications are set, the system achieves efficient accumulation of memory access information with minimal tracking overhead.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS8762684B2Hardware assistance for page table coherence with guest page mappings

Publication Date: 2014.06.24 VMWARE INC

AI summary

Some embodiments of the present invention include a memory management unit (MMU) configured to, in response to a write access targeting a guest page mapping of a guest virtual page number (GVPN) to a guest physical page number (GPPN) within a guest page table, identify a first page mapping that associates the GVPN with a physical page number (PPN). The MMU is also configured to determine whether a traced write indication is associated with the first page mapping and, if so, record update information identifying the targeted guest page mapping. The update information is used to reestablish coherence between the guest page mapping and the first page mapping. The MMU is further configured to perform the write access.