Memory Management Unit Offloading Page Table Walks
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Solution Overview
Problem
In multi-core processor chips, frequent access to memory devices by processor cores to obtain physical addresses causes a communication burden due to the need for multiple-level page table queries, leading to inefficiencies in the on-chip communication network.
Innovation Solution
A memory management unit packs necessary information for page table walk operations into data packets and sends them to an on-chip router, allowing the memory control device on the processor chip to execute these operations instead of the memory management units, reducing the burden on the on-chip communication network and increasing efficiency by minimizing interactions between memory management units and memory control devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory management units execute page table walk operations individually, then address translation can be performed, but the communication burden on the on-chip network increases due to multiple repeated accesses
Solution Approach 1:
The patent merges multiple identical page table walk operations from different memory management units into a single shared execution resource. When multiple MMUs need to perform page table walks, their operations are consolidated and executed by one MMU, reducing redundant communications with the on-chip network while maintaining address translation capability for all cores.
Solution Approach 2:
The patent introduces a shared page table walk execution mechanism as an intermediary between multiple MMUs and the on-chip network. This intermediary consolidates page table walk requests and performs them through a single communication channel, acting as a mediator that reduces the overall communication burden while still serving all MMU address translation needs.
2Adaptability or versatility
If multiple-level page tables are queried to obtain physical addresses, then virtual memory management is achieved, but the number of memory device accesses increases
Solution Approach 1:
The patent implements preliminary action by pre-fetching and caching page table data in the Translation Lookaside Buffer (TLB) before it is actually needed. When virtual addresses are accessed, the system checks the TLB first for previously cached translations, avoiding the need to perform complete multi-level page table walks and reducing memory access time.
Solution Approach 2:
The patent employs a nested structure with multiple levels of caching: the TLB provides L1 caching for frequent translations, while the multi-level page table structure provides L2 caching in memory. This nested arrangement allows the system to handle virtual memory management requirements while minimizing actual memory device accesses by satisfying many translation requests from the faster TLB layer.
Data Source
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AI summary
Embodiments of the present invention disclose a data processing method, including: receiving, by a memory management unit, a virtual address; determining, by the memory management unit, that the virtual address does not hit a translation look-aside buffer, and reading a page table base address register to obtain a page table base address; obtaining, by the memory management unit according to the page table base address, an identifier ID of a memory control device corresponding to the page table base address, sending the virtual address, the page table base address, and the ID of the memory control device to the memory control device; and receiving, by the memory management unit, a physical address that is sent by the memory control device and that is corresponding to the virtual address, and updating the translation look-aside buffer according to the physical address. In the data processing method, a page table walk operation is executed by only a memory control device, thereby reducing a burden caused by the page table walk operation to an on-chip communications network.