Multithreaded MMU Parallel Translation and Transaction Reordering
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Solution Overview
Problem
Conventional memory management units (MMUs) are limited by their ability to process only one translation table walk at a time, leading to performance degradation due to the serial handling of multiple client input transactions, which results in stalled operations and inefficient use of resources.
Innovation Solution
A multithreaded MMU is designed to process multiple address translation requests in parallel, utilizing multiple translation table walkers and schedulers to perform concurrent translations and transaction reordering, along with pre-filtering and post-filtering techniques to reduce redundancy and bandwidth consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single translation table walker is used to service translation requests, then the device complexity is reduced, but the productivity decreases due to serial processing of transactions
Solution Approach 1:
The patent divides the single translation table walker into multiple parallel walkers (TTW0, TTW1, etc.), each capable of independently servicing translation requests. This segmentation enables concurrent processing of multiple transactions, directly increasing throughput while maintaining manageable complexity through modular architecture
Solution Approach 2:
The patent transitions from serial processing (one-dimensional time sequence) to parallel processing by adding multiple translation walkers operating simultaneously. This dimensional change from single-threaded to multi-threaded architecture enables concurrent translation operations without proportionally increasing system complexity
2Loss of time
If transactions are processed in strict queue order, then the reliability of transaction ordering is maintained, but the loss of time increases due to stalled operations when translation cache misses occur
Solution Approach 1:
The patent implements speculative execution where translation requests are issued to multiple walkers in advance without waiting for previous requests to complete. Transactions are pre-loaded into the translation cache proactively, reducing wait times while maintaining ordering through subsequent validation mechanisms
Solution Approach 2:
The patent introduces dynamic transaction reordering capability that allows the system to adaptively adjust processing order based on translation cache hit/miss patterns. When a translation cache miss occurs, the system can stall only the affected transaction while allowing others to proceed, dynamically balancing ordering requirements with throughput optimization
3Productivity
If multiple translation table walkers are deployed for parallel processing, then the productivity increases, but the loss of substance increases due to duplication of translation requests and cache fills
Solution Approach 1:
The patent merges translation requests that target the same translation cache set before issuing them to multiple walkers. By combining duplicate requests and sharing translation cache fills across walkers, the system maintains parallel processing capability while reducing redundant memory accesses and bandwidth consumption
Solution Approach 2:
The patent implements a shared translation cache structure where translation entries are copied to multiple cache ways or replicated across walkers. This allows multiple walkers to operate in parallel while sharing the same translation data, eliminating redundant cache fills and reducing overall bandwidth consumption
Data Source
AI summary
Systems and methods relate to performing address translations in a multithreaded memory management unit (MMU). Two or more address translation requests can be received by the multithreaded MMU and processed in parallel to retrieve address translations to addresses of a system memory. If the address translations are present in a translation cache of the multithreaded MMU, the address translations can be received from the translation cache and scheduled for access of the system memory using the translated addresses. If there is a miss in the translation cache, two or more address translation requests can be scheduled in two or more translation table walks in parallel.


