MMU Partitioned Translation Cache for Thrashing Reduction

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Solution Overview

Problem

In computing systems, shared memory management units (MMUs) experience performance degradation due to 'thrashing' caused by competition among upstream devices for limited translation cache entries, which can negate the performance benefits of caching.

Innovation Solution

Implementing partitioned translation caches within the MMU, using a partition descriptor table and optional remapping and selection tables to identify and manage separate partitions for each device, reducing competition and optimizing cache operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a larger translation cache is used to mitigate inter-device competition, then cache hit rate and performance are improved, but power consumption and physical footprint increase

Engineering Contradiction:
ImproveMMU performanceVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The translation cache is segmented into multiple partitions, each assigned to specific upstream devices or device types. This segmentation allows each device to access a dedicated subset of cache entries, reducing inter-device competition and thrashing while maintaining a smaller overall cache size. The partition descriptor table stores metadata for each partition, enabling the MMU to route translation requests to the appropriate partition without requiring a large unified cache.

Inventive Principle:
Principle #1Segmentation

2Productivity

If a larger translation cache is used to mitigate inter-device competition, then cache hit rate and performance are improved, but physical footprint increases

Engineering Contradiction:
ImproveMMU performanceVSAvoidphysical footprint
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The translation cache is segmented into multiple partitions, each assigned to specific upstream devices or device types. This segmentation allows each device to access a dedicated subset of cache entries, reducing inter-device competition and thrashing while maintaining a smaller overall cache size. The partition descriptor table stores metadata for each partition, enabling the MMU to route translation requests to the appropriate partition without requiring a large unified cache.

Inventive Principle:
Principle #1Segmentation

3Device complexity

If a single shared translation cache is used, then device complexity is minimized, but thrashing occurs reducing performance

Engineering Contradiction:
ImproveMMU structureVSAvoidMMU performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The translation cache is segmented into multiple partitions, each assigned to specific upstream devices or device types. This segmentation allows each device to access a dedicated subset of cache entries, reducing inter-device competition and thrashing while maintaining a smaller overall cache size. The partition descriptor table stores metadata for each partition, enabling the MMU to route translation requests to the appropriate partition without requiring a large unified cache.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The partition descriptor table acts as an intermediary structure that manages the mapping between upstream devices and translation cache partitions. It stores partition descriptors that define which devices can access which partitions, enabling the MMU to efficiently route translation requests without direct device-to-cache conflicts. This intermediary layer adds minimal complexity while effectively preventing thrashing.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP3304321B1Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media
Publication Date: 2023.09.20 QUALCOMM INC
  • EP3304321B1 patent drawingFigure 1
  • EP3304321B1 patent drawingFigure 2
  • EP3304321B1 patent drawingFigure 3A~3B

AI summary

Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, in one aspect, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.