MMU Prefetch Logic for SoC Translation Latency
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Solution Overview
Problem
The inefficiency of virtual memory address translation in System on Chip (SoC) devices due to bottlenecks in memory management units (MMUs) when multiple masters share a common physical memory, leading to latency and resource consumption issues.
Innovation Solution
Implementing a multiple port memory management unit (MMU) with translation buffer units (TBUs) that include translation lookaside buffer (TLB) circuits and TLB prefetch logic to proactively generate address translation prefetch requests, decoupling prefetch generation from external control and allowing customizable options for each port, thereby populating TLBs independently and efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If virtual memory address translation is performed using a conventional MMU with multiple masters sharing common physical memory, then memory sharing capability is achieved, but translation latency and bottleneck efficiency occur
Solution Approach 1:
The patent divides the MMU into multiple independent Translation Buffer Units (TBUs), each handling translation for a specific master. This segmentation allows parallel translation operations across different masters, eliminating the sequential bottleneck and reducing translation latency while maintaining memory sharing capability.
Solution Approach 2:
The patent implements TLB prefetch logic that proactively loads translation entries into the TLB before they are actually needed by the masters. By performing preliminary translation and caching actions, the system anticipates future translation needs and reduces wait time when masters require address translation.
2Device complexity
If a conventional MMU processes translation requests sequentially, then device complexity is reduced, but productivity and translation throughput decrease
Solution Approach 1:
The MMU is segmented into multiple TBUs that can operate independently and simultaneously. Each TBU processes translation requests for its assigned master, enabling parallel throughput improvement without requiring a fundamentally complex MMU architecture. The segmented design maintains relative simplicity while achieving high productivity.
Solution Approach 2:
Each TBU includes integrated TLB prefetch logic that autonomously monitors access patterns and initiates prefetch operations without external control. This self-service capability allows each TBU to optimize its own translation throughput independently, increasing overall system productivity without adding centralized control complexity.
3Ease of operation
If TLB prefetching is controlled externally, then coordination between multiple masters is simplified, but prefetch responsiveness and customization for each port are reduced
Solution Approach 1:
The prefetch control functionality is segmented and distributed to each TBU individually. Each TBU's prefetch logic independently monitors its own port's access patterns and generates prefetch requests tailored to that port's specific needs. This segmentation enables full customization per port while maintaining simple operation through autonomous local control.
Solution Approach 2:
Each TBU's prefetch logic serves itself by autonomously detecting access patterns and generating appropriate prefetch requests without external intervention. This self-service approach maximizes prefetch responsiveness to port-specific workloads and enables customization for each port while eliminating the need for complex external coordination mechanisms.
4Quantity of substance
If translation entries are loaded on-demand into TLB, then memory bandwidth is conserved, but translation latency increases due to misses
Solution Approach 1:
The TLB prefetch logic proactively loads translation entries into the TLB before they are actually requested by masters. By performing preliminary loading based on predicted access patterns, the system reduces translation latency from TLB misses while consuming memory bandwidth only for anticipated translations, optimizing the trade-off between bandwidth usage and translation speed.
Solution Approach 2:
The prefetch logic continuously monitors actual memory access patterns and uses this feedback to adjust prefetch decisions. By incorporating feedback from real usage, the system prefetches only entries that are likely to be needed, conserving memory bandwidth while ensuring that high-probability translation requests are already cached, thereby reducing translation latency.
Data Source
AI summary
A memory management unit circuit includes a plurality of ports with a plurality of translation buffer units. Each translation buffer unit includes a translation lookaside buffer circuit and a translation logic circuit configured to perform virtual to physical address translation using the translation lookaside buffer circuit. A translation lookaside buffer circuit prefetch logic circuit monitors virtual memory access requests received at the corresponding port of the memory management unit circuit and detects satisfaction of at least one trigger condition. In response, address translation prefetch requests are generated. A control circuit transmits the address translation prefetch requests to a physical memory circuit and receives address translation data for populating the translation lookaside buffer.