Memory Management Unit Queuing Page Walks for Faster Translation
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Solution Overview
Problem
The speed of page table walks is slower than processor processing speed, causing a bottleneck that reduces system performance, especially in processors performing massive parallel operations.
Innovation Solution
A memory management unit (MMU) with a translation lookaside buffer (TLB) caches page table entries and a page table walk request queue, utilizing one or more page table walkers (PTWs) to process associated page table walk requests for PTEs stored in the same memory cell row, thereby increasing the row buffer hit rate and reducing processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If frequent page table walks are performed to convert virtual addresses to physical addresses, then address conversion is achieved, but processing speed is reduced due to the slow walk speed compared to processor processing speed
Solution Approach 1:
The patent applies preliminary action by pre-fetching and caching page table entries in the TLB before they are actually needed for address conversion. This allows the processor to perform address translation without waiting for the slow page table walk process, thereby reducing the time loss and improving overall productivity.
Solution Approach 2:
The patent introduces an intermediary mechanism (the TLB cache) between the processor and the main memory page table. This intermediary stores pre-fetched page table entries, allowing fast address conversion without directly accessing the slow main memory page table structure, thus resolving the speed mismatch between processor and page table walk.
2Productivity
If page table walk requests are processed sequentially, then simple processing logic is maintained, but system performance is reduced due to bottlenecks in massive parallel operations
Solution Approach 1:
The patent applies segmentation by dividing the page table walk processing into multiple independent units (PTWs - Page Table Walker units) that can process requests in parallel. Each PTW handles a subset of page table walk requests, allowing the system to maintain simple individual processing logic while achieving high system performance through parallelization.
Solution Approach 2:
The patent transitions from sequential processing to parallel processing by adding a temporal dimension to the processing architecture. Multiple PTWs operate simultaneously on different page table walk requests, transforming the single-dimensional sequential process into a multi-dimensional parallel process, thereby improving system performance without excessive complexity increase.
Data Source
AI summary
A memory management unit includes a TLB configured to cache PTEs including a mapping between a virtual and a physical frame number, and to convert a virtual address into a physical address using the cached PTEs. A page table walk request queue is configured to queue page requests corresponding to a virtual page number when a TLB miss is occurred, and one or more PTWs are configured to acquire a PTE from the main memory, and to convert the virtual page numbers into physical frame numbers using the PTE. A PTW is configured to select associated page table walk requests having the same base address of corresponding virtual page numbers, to consecutively provide cache line requests for acquiring PTEs corresponding to the associated page table walk requests, to acquire the PTEs corresponding to the associated PTE requests, and to provide the acquired PTEs to the TLB.