MMU Sensitive Access Handling for Virtual Memory Security
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Solution Overview
Problem
Current microprocessor security mechanisms are inadequate in preventing rogue applications from bypassing hierarchical protection mechanisms, necessitating a supplementary security system to ensure secure memory access.
Innovation Solution
A memory management unit (MMU) with a translation lookaside buffer (TLB) and sensitive access handling, utilizing a sensitive access enable bit and recency bit to generate interrupts for sensitive memory access, and invoking a chaperoned execution handler to validate memory access, particularly for pages containing personally identifying or financial information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a hierarchical protection mechanism is implemented in the operating system, then security for memory access is improved, but it can be defeated by rogue applications
Solution Approach 1:
The patent segments the security mechanism into two independent layers: the traditional operating system hierarchical protection mechanism and a new hardware-based MMU protection mechanism. Each layer operates independently with its own protection rules, so that compromise of one layer does not necessarily compromise the entire security system. The MMU maintains separate protection rings and access control lists that are independent from OS-level security.
Solution Approach 2:
The patent implements preemptive security measures by introducing a secondary protection mechanism that activates before unauthorized access can occur. The MMU continuously monitors and validates memory access requests against stored access control policies, preventing rogue applications from bypassing security even if they exploit OS vulnerabilities. This cushioning layer ensures that security violations are blocked at the hardware level rather than allowing them to propagate.
2Reliability
If a secondary security mechanism is added to the MMU, then security reliability is improved, but device complexity increases
Solution Approach 1:
The patent designs the MMU to perform multiple functions: traditional virtual-to-physical address translation and the new security validation function. By integrating access control list storage, protection ring management, and security policy enforcement within the existing MMU architecture, the patent avoids adding separate hardware components. This multi-functionality approach achieves enhanced security while minimizing increases in device complexity.
Solution Approach 2:
The MMU is designed to autonomously validate memory access requests against stored access control policies without requiring constant intervention from the operating system or external security modules. The MMU independently checks protection rings, validates virtual addresses, and enforces security rules, reducing the complexity burden on the overall system by making the security mechanism self-contained and self-managing.
3Reliability
If strict security validation is performed on all memory accesses, then security is improved, but processing speed decreases
Solution Approach 1:
The patent implements selective security validation rather than universal validation. The MMU applies strict security checks only to memory accesses that require protection based on access control policies, while allowing unrestricted access for validated requests. This partial action approach ensures security for sensitive operations without imposing validation overhead on all memory accesses, thereby maintaining high processing speed for normal operations.
Solution Approach 2:
The patent performs security validation in advance by pre-configuring access control lists and protection ring settings in the MMU before memory access operations begin. The MMU is pre-loaded with security policies and authorization rules, enabling it to quickly validate access requests without performing complex security checks during actual memory operations. This preliminary preparation reduces the time penalty for security validation.
Data Source
AI summary
A disclosed method includes obtaining a physical address corresponding to a virtual address responsive to detecting a virtual address associated with a memory access instruction and, responsive to identifying a memory page associated with the physical address as a sensitive memory page, evaluating sensitive access information associated with the memory page. If the sensitive access information satisfies a sensitive access criteria, invoking a sensitive access handler to control execution of the memory access instruction.


