MMU Speculative Table Walk Queue for TLB Miss Handling
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Solution Overview
Problem
Modern microprocessors face performance issues due to the resource-intensive page table walks triggered by translation look-aside buffer (TLB) misses, which interfere with other memory access operations and reduce system performance.
Innovation Solution
A processor with a memory management unit (MMU) that detects the oldest uncompleted memory access operation and stores demand table walk requests in a queue, allowing speculative requests to be stored only when resources are underutilized, thereby minimizing interference with TLB hits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If page table walks are performed for TLB misses, then address translation is completed, but memory subsystem resources are consumed and performance of other memory access operations is reduced
Solution Approach 1:
The patent performs page table walks in advance when memory resources are underutilized, storing results in a queue before they are needed. This preliminary action allows the translation to be completed and cached before subsequent memory access operations require it, thereby avoiding resource contention when the actual memory access occurs.
Solution Approach 2:
The patent introduces a page table walk queue as an intermediary structure between the memory subsystem and the address translation process. This queue buffers the page table walk operations, decoupling them from the main memory access operations and preventing direct resource contention while ensuring translations are available when needed.
2Speed
If speculative page table walks are performed, then translation speed is improved, but memory system resources are further acquired and interference with TLB hit operations increases
Solution Approach 1:
The patent dynamically adjusts the performance of speculative page table walks based on current memory subsystem utilization. When memory resources are underutilized, speculative walks are permitted to improve translation speed. When resources are heavily utilized, speculative walks are suppressed or deferred to the queue, thereby dynamically balancing translation speed against interference with other memory operations.
Solution Approach 2:
The patent changes the operational parameters of speculative page table walks based on system state. The key parameter changed is the authorization to perform speculative walks, which is enabled when memory utilization is low and disabled or deferred when utilization is high. This parameter change allows the system to optimize translation speed when possible while preventing interference when resources are constrained.
Data Source
AI summary
A system and method for efficiently handling translation look-aside buffer (TLB) misses. A memory management unit (MMU) detects when a given virtual address misses in each available translation-lookaside-buffer (TLB). The MMU determines whether a memory access operation associated with the given virtual address is the oldest, uncompleted memory access operation in a scheduler. If this is the case, a demand table walk (TW) request may be stored in an available entry in a TW queue. During this time, the utilization of the memory subsystem resources may be low. While a demand TW request is stored in the TW queue, subsequent speculative TW requests may be stored in the TW queue. When the TW queue does not store a demand TW request, no more entries of the TW queue may be allocated to store TW requests.