Millimeter-Wave Frequency Synthesizer With Auto Lock-Reacquisition
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing millimeter wavelength frequency synthesizer designs face issues with high noise and power consumption due to the use of injection-locked frequency dividers and limited locking range, and they often require complex optimization to minimize residual noise.
Innovation Solution
A frequency synthesizer system that includes an intermediate-frequency (IF) synthesizer, a sub-sampling phase-locked loop (SSPLL), and a sub-sampling lock detector (SSLD) to automatically switch between low-noise normal-operating and frequency-acquisition modes, using a pseudo-digital state machine and multiplexer to manage the input signal and ensure locking to a target frequency with reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If injection-locked frequency dividers (ILFDs) are used to facilitate operation at millimeter wavelengths, then the frequency synthesizer can operate at high frequencies, but power consumption increases significantly
Solution Approach 1:
The frequency synthesis process is divided into two stages: a first-stage conventional PLL operating at lower frequency to generate intermediate frequency, and a second-stage SSPLL operating at millimeter wavelengths. This segmentation allows the high-frequency ILFD to be replaced with digital circuitry in the first stage, reducing power consumption while maintaining millimeter-wave operation capability in the second stage.
Solution Approach 2:
An intermediate frequency (IF) signal is introduced as a mediator between the reference frequency and the millimeter-wave output. The IF signal serves as an intermediate carrier that can be generated at lower frequencies using power-efficient digital dividers, then upconverted to millimeter wavelengths by the SSPLL, avoiding the need for continuous high-frequency operation.
2Speed
If injection-locked frequency dividers (ILFDs) are used, then high-frequency operation is enabled, but locking range becomes limited
Solution Approach 1:
The frequency synthesis is segmented into two cascaded PLL stages, each with its own frequency divider operating at different frequency ranges. The first-stage divider operates at lower frequencies with wider locking range, while the second-stage operates at millimeter wavelengths. This segmentation allows each stage to operate within its optimal locking range, expanding the overall system's adaptability.
3Use of energy by moving object
If a first-stage conventional PLL is used to generate intermediate frequency, then power consumption is reduced, but residual noise is generated that increases design complexity
Solution Approach 1:
A lock detector is implemented to monitor the locking status of the SSPLL and provide feedback control. When the SSPLL achieves lock, the system switches the reference input from the IF signal to the original reference frequency, automatically minimizing the noise contribution from the first-stage PLL. This feedback mechanism simplifies the design by eliminating the need for complex manual optimization of bandwidth and IF values.
Solution Approach 2:
The system dynamically switches between two operating modes: during frequency acquisition, the SSPLL uses the IF signal as reference to ensure wide locking range; during normal operation, it switches to using the original reference frequency to minimize noise. This dynamic adaptation allows the system to optimize performance based on operational state without requiring fixed complex design parameters.
4Object-generated harmful factors
If the IF signal frequency is set high to minimize residual noise, then noise contribution is reduced, but the design complexity of the sub-sampling phase detector increases
Solution Approach 1:
The system dynamically adjusts the reference input to the SSPLL based on operational state. During frequency acquisition, a higher IF frequency is used to minimize noise; during normal operation, the system switches to using the original reference frequency. This dynamic switching, controlled by the lock detector, allows the system to achieve low noise performance without permanently increasing the design complexity of the sub-sampling phase detector.
Data Source
AI summary
The system includes an intermediate-frequency (IF) synthesizer that generates an IF signal based on a reference signal, and a sub-sampling PLL (SSPLL) that generates a high-frequency output signal based on an input. A switch selects either the reference signal or the IF signal to be the input to the SSPLL. When the reference signal is the input to the SSPLL, the frequency synthesizer operates in a low-noise normal-operating mode, and when the IF signal is the input to the SSPLL, the frequency synthesizer operates in a higher-noise, frequency-acquisition mode. A sub-sampling lock detector (SSLD) determines whether the frequency synthesizer becomes unlocked during the normal-operating mode, and if so, activates the switch to move the system into the frequency-acquisition mode. It also determines whether the frequency synthesizer becomes relocked to the target frequency during the frequency-acquisition mode, and if so, activates the switch to move the system into the normal-operating mode.