Dithered M/N Clock Divider Using Cyclic Seed Rotation for Spur Control
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Solution Overview
Problem
Multifunctional integrated circuits (ICs) face challenges in supporting multiple sampling rates and clock frequencies, leading to coupling spurs and degradation of spurious free dynamic range (SFDR) due to digital activity coupling with analog activity, particularly in fractional clock division scenarios where brute force dithering becomes infeasible for complex M/N ratios.
Innovation Solution
A method for dithering fractional clock dividers is introduced, using a clock enable sequence generator that generates cyclic rotations of a seed pattern, distributed across high frequency clock edges, employing a cyclic shift register, selector logic, and random number generation to uniformly distribute low frequency digital activity, effectively eliminating signal spurs without requiring extensive lookup tables for each M/N ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If brute force dithering is used for fractional clock division, then signal spurs can be eliminated, but device complexity and memory requirements increase significantly due to extensive lookup tables needed for complex M/N ratios
Solution Approach 1:
The patent segments the dithering process into two independent parts: (1) generating a base clock enable sequence using a simple counter and comparator, and (2) randomizing the sequence by cyclically shifting it based on random values. This segmentation eliminates the need for extensive lookup tables while maintaining spur reduction effectiveness.
Solution Approach 2:
The patent performs preliminary generation of a deterministic clock enable sequence using a simple counter that counts from 0 to N-1 and compares with M. This preliminary sequence is then randomized through cyclic shifting, avoiding the need to pre-compute and store all possible dithered sequences in lookup tables.
2Adaptability or versatility
If multiple dock frequencies are supported in the same IC, then multifunctionality is improved, but coupling spurs and SFDR degradation occur due to digital activity coupling to analog activity
Solution Approach 1:
The patent applies periodic dithering where the clock enable sequence is randomized at regular intervals (every N clock cycles) by introducing new random shift values. This periodic randomization distributes digital activity uniformly across all high frequency clock edges, eliminating coupling spurs while supporting multiple sampling rates.
Solution Approach 2:
The patent changes the temporal distribution parameter of the clock enable signal by randomly shifting the base sequence. This parameter change (cyclic shifting) redistributes the digital switching activity across different time instances, preventing coherent coupling between digital and analog domains while maintaining the required clock division ratio.
3Object-affected harmful factors
If randomized clock division is applied, then low frequency digital activity is distributed randomly on high frequency clock edges, but implementation complexity increases for fractional M/N ratios
Solution Approach 1:
The patent merges the deterministic clock division function (counter + comparator) with the randomization function (cyclic shift register controlled by random values) into a unified dithered clock divider. This merging achieves spur reduction without requiring separate complex lookup table structures or multiple independent circuits.
Solution Approach 2:
The patent replaces the mechanical/memory-intensive approach of brute force dithering (extensive lookup tables) with a computational approach using simple counters, comparators, and cyclic shift operations driven by random number generators. This substitution dramatically reduces hardware complexity while maintaining effectiveness.
Data Source
AI summary
A method for dithering a fractional clock divider includes generating a first clock enable sequence based on a seed pattern of M ones and N minus M zeros, selecting a cyclic rotation of the seed pattern after N input clock cycles, and generating a second clock enable sequence based on the cyclic rotation. A clock gate receives the input clock signal and the clock enable sequences and outputs M clock cycles for every N input clock cycles. A random number generator indicates the cyclic rotation of the seed pattern. The seed pattern can be replaced with an updated seed pattern of M ones and N minus M zeros in a different order. In some examples, the clock enable sequence is generated using a cyclic shift register containing the seed pattern and a multiplexor. In other examples, the clock enable sequence is generated using a modulo N counter and a comparator.