Mobile SoC Tile Addressing for Compressed Multimedia Access
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Solution Overview
Problem
Existing processor architectures face challenges in efficiently accessing and processing compressed multimedia data, particularly in scenarios requiring high throughput and large memory capacity, as they struggle with managing dependencies and hazards in accessing compressed multimedia traffic.
Innovation Solution
The solution involves converting a cache line address into a two-dimensional address based on a stride width, transforming this address into a pixel address, and computing a tile address using image attributes and main memory configuration, while incorporating modules for hazard detection and data retrieval from compressed memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If compressed multimedia data is stored in main memory to reduce storage demands, then storage capacity is improved, but processor access speed and throughput deteriorate due to complex address translation and hazard management
Solution Approach 1:
The system pre-computes tile addresses from cache line addresses using the tile address computation module before actual data access occurs. Image attributes including compression ratios are pre-loaded into the image attributes cache module. This preliminary preparation eliminates complex computations during actual processor access, thereby maintaining high throughput while storing compressed data in main memory.
Solution Approach 2:
The patent introduces an intermediary address translation mechanism that maps cache line addresses to tile addresses in compressed memory through intermediate calculations involving stride width and pixel addresses. This intermediary translation layer simplifies the access path between processor and compressed storage, improving throughput despite the increased storage capacity requirement.
2Quantity of substance
If address translation from cache line address to tile address is performed in real-time, then storage efficiency is improved, but processing time increases due to multiple computation steps
Solution Approach 1:
The tile address computation module performs address translation computations in advance, converting cache line addresses to tile addresses before actual data retrieval. The image attributes cache module stores pre-computed image attributes such as compression ratios and stride widths. This preliminary computation approach maintains storage efficiency while minimizing processing time during actual access operations.
3Reliability
If hazard detection and request segregation are implemented to manage read-write dependencies, then data reliability is improved, but device complexity increases due to additional modules
Solution Approach 1:
The hazard management functionality is segmented into a dedicated tile hazard module that operates independently from the main address computation and data retrieval paths. This module specifically handles read-write dependency detection and request segregation. By segmenting the hazard detection function, the system achieves improved data reliability while containing the increase in device complexity to a specialized, isolated component.
4Measurement precision
If stride width and pixel address transformations are computed for every access, then address precision is improved, but computational overhead increases
Solution Approach 1:
The system pre-computes and caches image attributes including stride width and pixel address transformations in the image attributes cache module. When a cache line address needs to be translated to a tile address, the pre-computed attributes are retrieved rather than recalculated. This preliminary computation approach maintains address precision while significantly reducing computational overhead during actual access operations.
Data Source
AI summary
Aspects of the disclosure are directed to processor access to compressed multimedia data. In accordance with one aspect, the disclosure includes converting a cache line address into a two-dimensional address based on a stride width; transforming the two-dimensional address into a pixel address; and computing a tile address using the pixel address and a main memory configuration.