Mode-Based Clock Class Setting for 5G TDD Stability

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Solution Overview

Problem

Current 5G base station time division duplexing (TDD) services face instability due to the loss of a master clock source, leading to network flapping and multiple switching times during the selection of a new clock source.

Innovation Solution

A clock class setting method that sets a higher clock class value in a locked mode and a lower value in an out-of-holdover mode to facilitate quick selection of a new clock source, reducing network switching times and instability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the clock device maintains the same clock class value in both locked mode and out-of-holdover mode, then the device complexity is reduced, but the network stability deteriorates due to multiple switching times and network flapping

Engineering Contradiction:
Improveclock class setting complexityVSAvoidnetwork stability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent applies dynamics by making the clock class value changeable based on the device's operational mode. The clock device dynamically adjusts its clock class value depending on whether it is in locked mode or out-of-holdover mode, allowing the system to adapt to different operational states and prevent unnecessary switching during clock source selection

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the clock class parameter value based on the device mode. Specifically, it sets the clock class to a first value when in locked mode and to a second value (different from the first value) when in out-of-holdover mode. This parameter differentiation enables the clock device to be prioritized or deprioritized in clock source selection depending on its operational state, thereby reducing network flapping

Inventive Principle:
Principle #35Parameter changes

2Loss of time

If the clock device quickly switches to a new clock source upon master clock loss, then the network recovery time is reduced, but the network stability worsens due to multiple switching times and flapping

Engineering Contradiction:
Improvenetwork recovery timeVSAvoidnetwork stability
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The patent implements feedback by monitoring the device mode (locked or out-of-holdover) and using this information to determine the clock class value. This feedback mechanism ensures that the clock device only becomes a preferred clock source when appropriate (when in out-of-holdover mode with a different clock class value), preventing premature or unnecessary switching while still enabling quick recovery when conditions are favorable

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20250293790A1Clock class setting method, device, and system
Publication Date: 2025.09.18 HUAWEI TECH CO LTD
  • US20250293790A1 patent drawing
  • US20250293790A1 patent drawing
  • US20250293790A1 patent drawing

AI summary

This application discloses a clock class setting method, a device, and a system. A clock device determines a clock class in a locked mode as a first value, and determines a clock class in an out-of-holdover mode as a second value, where the first value is greater than the second value. If the clock device enters the out-of-holdover mode from the locked mode, the clock device changes the clock class from the first value to the second value.