Mode Based Skew for Scan Test Voltage Drop Reduction
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Solution Overview
Problem
During scan testing in integrated circuits, simultaneous switching of circuits leads to significant instantaneous voltage drops and peak current consumption, which existing technologies fail to mitigate effectively without increasing test time or requiring separate testing of functional circuit blocks.
Innovation Solution
Implementing mode-based skew by using multiple clock-gating circuits within functional circuit blocks to apply different delays to clock signals, allowing circuits to switch at different times and reducing instantaneous voltage drops and peak current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If simultaneous switching of circuits is used during scan testing, then test efficiency is improved, but instantaneous voltage drop and peak current consumption increase
Solution Approach 1:
The patent segments the simultaneous switching event into multiple time-staggered switching events by introducing skew to clock signals. Different functional circuit blocks are switched at different times rather than simultaneously, dividing the large instantaneous current demand into smaller, distributed current demands over time.
Solution Approach 2:
The patent employs periodic skew patterns in clock signal distribution to create a rhythmic, distributed switching schedule. By periodically varying the clock signal timing across different blocks, the system achieves both high test efficiency and reduced peak current consumption through controlled temporal distribution of switching events.
2Loss of energy
If clock signals are skewed to different functional circuit blocks, then instantaneous voltage drop is reduced, but clock signal distribution complexity increases
Solution Approach 1:
The patent applies local quality by introducing skew specifically to clock signals destined for different functional circuit blocks during scan testing, while leaving other clock signals unaffected. This localized application of skew targeted at problem areas achieves voltage drop reduction without requiring system-wide clock distribution redesign.
Solution Approach 2:
The patent implements dynamic clock signal skew that can be adjusted based on testing requirements. The skew amounts and timing are optimized for scan testing operations, allowing the clock distribution system to adapt its behavior dynamically rather than requiring fixed, complex hardware modifications.
3Loss of energy
If multiple clock-gating circuits with different delays are used, then peak current consumption is reduced, but circuit complexity increases
Solution Approach 1:
The patent makes clock-gating circuits multi-functional by enabling them to perform both their traditional power-saving gating function and an additional function of introducing controlled skew during scan testing. This universal design allows existing clock-gating infrastructure to serve dual purposes, reducing peak current without requiring entirely separate skew-generation circuitry.
Solution Approach 2:
The patent utilizes parameter changes in clock-gating circuits by varying the delay parameters of existing circuits to achieve skew effects. Rather than adding new circuit elements, the system modifies operational parameters (delay values) of existing clock-gating circuits to create the desired temporal distribution of switching events.
Data Source
AI summary
A method and apparatus for implementing mode based skew is disclosed. In one embodiment, an IC includes a number of different functional units each coupled to receive a respective one of a number of different clock signals. One or more of the functional circuit blocks includes at least two clock-gating circuits that are coupled to receive the clock signal provided to that functional circuit block. During a scan test, a first clock-gating circuit within a functional circuit block is configured to provide a first delay to the clock signal. A second clock-gating circuit within the functional circuit block may provide a second delay to the clock signal, the second delay being different from the first.