Mode Register Activate Sequence for Memory Address Extension

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Solution Overview

Problem

Existing memory devices face challenges in transmitting additional activate information without increasing the number of command/address (CA) bus pins, extending the activate cycle count, or impacting die size, which is necessary for emerging memory technologies with increased density and dynamic page size activation features.

Innovation Solution

The use of mode registers to transmit additional activate information to memory devices, allowing for the activation of more row addresses without modifying the ACT commands or increasing the number of CA bus pins, thereby maintaining system performance and reducing the impact on die size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If additional activate information is transmitted using existing ACT commands, then memory device compatibility is maintained, but the number of CA bus pins must be increased

Engineering Contradiction:

Improvememory device compatibilityVSAvoidnumber of CA bus pins

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent makes existing CA bus pins perform multiple functions by using them to transmit both traditional ACT command information and additional activate information such as row address extension bits and dynamic page size indicators, eliminating the need for additional pins

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent changes the parameters of existing ACT commands by modifying the address table mappings and command encoding to accommodate additional activate information within the same command structure, allowing flexible configuration of page sizes and row addresses

Inventive Principle:

Principle #35Parameter changes

2Loss of information

If additional activate information is transmitted by extending the ACT command cycle, then information capacity increases, but system performance deteriorates

Engineering Contradiction:

Improveactivate information capacityVSAvoidsystem performance

Core Design Contradiction:

Loss of informationVSProductivity

Solution Approach 1:

The patent segments the activate information into multiple fields within the existing ACT command structure, including bank address, row address, and additional fields for row address extension bits and dynamic page size indicators, allowing comprehensive information transmission without extending the command cycle

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent adds information in a different dimension by utilizing unused or underutilized address bits and command fields rather than extending the temporal dimension (command cycle length), thereby maintaining performance while increasing information capacity

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Loss of information

If additional activate information is transmitted using more clock cycles, then information transmission is complete, but activate cycle count increases

Engineering Contradiction:

Improveactivate information transmissionVSAvoidactivate cycle count

Core Design Contradiction:

Loss of informationVSLoss of time

Solution Approach 1:

The patent merges the transmission of additional activate information with the existing ACT command by combining row address extension bits and dynamic page size indicators into the same command cycle, eliminating the need for separate transmission cycles

Inventive Principle:

Principle #5Merging (Combining)

4Adaptability or versatility

If dynamic page size activation feature is provided, then controller flexibility increases, but additional activate information must be transmitted

Engineering Contradiction:

Improvecontroller flexibilityVSAvoidadditional activate information

Core Design Contradiction:

Adaptability or versatilityVSLoss of information

Solution Approach 1:

The patent prepares the additional activate information including dynamic page size indicators and row address extension bits in advance within the ACT command structure, making them ready for transmission without requiring additional communication overhead

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250201285A1Extended address interface activate sequence using mode register write

Publication Date: 2025.06.19 MICRON TECHNOLOGY INC

AI summary

A method and a device is provided for implementing a mode register to transmit additional activate information to a memory device. Additional activate information may be transmitted to the memory device without increasing the tRCD time, or increasing the command/address (CA) bus pins, or adding additional circuit area, thereby reducing the impact on the performance of the memory device.