Mode Register Buffering for Delay-Free Memory Bank I/O

Solution Overview

Problem

Existing memory devices experience input/output delays due to the use of the same channel for accessing mode registers and memory banks, leading to performance deterioration when frequent access to mode registers occurs.

Innovation Solution

Incorporation of a mode register buffer array that buffers input/output operations independently from the memory bank channel, allowing simultaneous data movement between the mode register buffer array and the mode register array without delaying memory bank operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the same channel is used for both mode register access and memory bank input/output operations, then the device complexity is reduced, but input/output delays occur and productivity deteriorates

Engineering Contradiction:

Improvechannel structureVSAvoidinput/output operation speed

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent divides the single shared channel into two separate independent channels: one channel dedicated for mode register access operations and another channel for memory bank input/output operations. This segmentation allows simultaneous independent operations on both channels, eliminating the mutual interference and delays that occurred when a single channel had to serve both purposes sequentially.

Inventive Principle:

Principle #1Segmentation

2Device complexity

If the same channel is used for both mode register access and memory bank operations, then device complexity is reduced, but loss of time occurs during mode register access

Engineering Contradiction:

Improvechannel structureVSAvoidinput/output delay

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The patent divides the single shared channel into two separate independent channels: one channel dedicated for mode register access operations and another channel for memory bank input/output operations. This segmentation allows simultaneous independent operations on both channels, eliminating the mutual interference and delays that occurred when a single channel had to serve both purposes sequentially.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The mode register buffer array pre-loads and caches mode register data, allowing the main channel to access pre-prepared data rather than waiting for real-time mode register operations. This preliminary preparation of data reduces the time loss during mode register access by having data ready in advance.

Inventive Principle:

Principle #10Preliminary action

3Adaptability or versatility

If frequent access to mode registers occurs through the shared channel, then adaptability is maintained, but productivity of memory bank operations deteriorates

Engineering Contradiction:

Improvemode register access capabilityVSAvoidmemory bank input/output speed

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent divides the single shared channel into two separate independent channels: one channel dedicated for mode register access operations and another channel for memory bank input/output operations. This segmentation allows simultaneous independent operations on both channels, eliminating the mutual interference and delays that occurred when a single channel had to serve both purposes sequentially.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The mode register buffer array acts as an intermediary between the mode register array and the main input/output channel. It caches mode register data and handles access requests, allowing the main channel to operate independently without being blocked by frequent mode register accesses, thus maintaining both adaptability and productivity.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20260031137A1Memory device and memory system including thereof

Publication Date: 2026.01.29 SAMSUNG ELECTRONICS CO LTD

AI summary

Disclosed is a memory device communicating with a host device. The memory device may comprise a plurality of memory banks, a mode register array including a plurality of mode registers, a first mode register buffer, including a first plurality of buffer bit fields, configured to load raw data provided from a target mode register, which is one of the plurality of mode registers, to the first plurality of buffer bit fields in response to a first command received from the host device, and an input/output circuit configured to output one or more target bits stored in the first plurality of buffer bit fields to the host device in response to a second command received from the host device.